dts: socfpga: Add support for SD/MMC on the SOCFPGA platform

Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.

Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Finally, fix an indentation error for the sysmgr node.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>

diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
new file mode 100644 (file)
index 0000000..4897bea
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
@@ -0,0 +1,23 @@
+* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile
+  Storage Host Controller
+
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific
+extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+       - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform
+
+Example:
+
+       mmc: dwmmc0@ff704000 {
+               compatible = "altr,socfpga-dw-mshc";
+               reg = <0xff704000 0x1000>;
+               interrupts = <0 129 4>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 537f1a5c07f55538ca161a16f8d0594b6170ca62..5f582467fccc2ae6101184f030292abfdce8ac0a 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -473,6 +473,17 @@
                        arm,data-latency = <2 1 1>;
                };
 
+               mmc: dwmmc0@ff704000 {
+                       compatible = "altr,socfpga-dw-mshc";
+                       reg = <0xff704000 0x1000>;
+                       interrupts = <0 139 4>;
+                       fifo-depth = <0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+                       clock-names = "biu", "ciu";
+               };
+
                /* Local timer */
                timer@fffec600 {
                        compatible = "arm,cortex-a9-twd-timer";
@@ -527,8 +538,8 @@
                };
 
                sysmgr@ffd08000 {
-                               compatible = "altr,sys-mgr";
-                               reg = <0xffd08000 0x4000>;
-                       };
+                       compatible = "altr,sys-mgr", "syscon";
+                       reg = <0xffd08000 0x4000>;
+               };
        };
 };

diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index a85b4043f888b108103ffe3dd3f06856c7e1d90a..6c87b7070ca77d0379e03b214a7a0f6601973bfc 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -27,6 +27,17 @@
                        };
                };
 
+               dwmmc0@ff704000 {
+                       num-slots = <1>;
+                       supports-highspeed;
+                       broken-cd;
+
+                       slot@0 {
+                               reg = <0>;
+                               bus-width = <4>;
+                       };
+               };
+
                serial0@ffc02000 {
                        clock-frequency = <100000000>;
                };

diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index a8716f6dbe2e0adaa365032510a128238be7a764..ca41b0ebf461b12a413d36627a73fff323f5d69a 100644 (file)
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -28,6 +28,17 @@
                        };
                };
 
+               dwmmc0@ff704000 {
+                       num-slots = <1>;
+                       supports-highspeed;
+                       broken-cd;
+
+                       slot@0 {
+                               reg = <0>;
+                               bus-width = <4>;
+                       };
+               };
+
                ethernet@ff702000 {
                        phy-mode = "rgmii";
                        phy-addr = <0xffffffff>; /* probe for phy addr */

diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index d1ec0cab2dee0daa986a8ddd75f10222cbcd25bb..222313f5420bbafe18968845a8bbe9e25c6b3ef1 100644 (file)
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,17 @@
                        };
                };
 
+               dwmmc0@ff704000 {
+                       num-slots = <1>;
+                       supports-highspeed;
+                       broken-cd;
+
+                       slot@0 {
+                               reg = <0>;
+                               bus-width = <4>;
+                       };
+               };
+
                ethernet@ff700000 {
                        phy-mode = "gmii";
                        status = "okay";