drm: rcar-du: Configure DPAD0 routing through last group on Gen3
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Mon, 26 Jun 2017 13:41:47 +0000 (16:41 +0300)
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Thu, 3 Aug 2017 13:17:24 +0000 (16:17 +0300)
On Gen3 SoCs DPAD0 routing is configured through the last CRTC group,
unlike on Gen2 where it is configured through the first CRTC group. Fix
the driver accordingly.

Fixes: 2427b3037710 ("drm: rcar-du: Add R8A7795 device support")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
drivers/gpu/drm/rcar-du/rcar_du_group.c

index a3e29bb420fd0f85c3197b06770c2a803098cc12..2f37ea901873b7b559b92ea9f0ceee7e66950955 100644 (file)
@@ -212,6 +212,9 @@ void rcar_du_group_restart(struct rcar_du_group *rgrp)
 
 int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
 {
+       struct rcar_du_group *rgrp;
+       struct rcar_du_crtc *crtc;
+       unsigned int index;
        int ret;
 
        if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS))
@@ -219,17 +222,22 @@ int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
 
        /*
         * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
-        * configured in the DEFR8 register of the first group. As this function
-        * can be called with the DU0 and DU1 CRTCs disabled, we need to enable
-        * the first group clock before accessing the register.
+        * configured in the DEFR8 register of the first group on Gen2 and the
+        * last group on Gen3. As this function can be called with the DU
+        * channels of the corresponding CRTCs disabled, we need to enable the
+        * group clock before accessing the register.
         */
-       ret = clk_prepare_enable(rcdu->crtcs[0].clock);
+       index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
+       rgrp = &rcdu->groups[index];
+       crtc = &rcdu->crtcs[index * 2];
+
+       ret = clk_prepare_enable(crtc->clock);
        if (ret < 0)
                return ret;
 
-       rcar_du_group_setup_defr8(&rcdu->groups[0]);
+       rcar_du_group_setup_defr8(rgrp);
 
-       clk_disable_unprepare(rcdu->crtcs[0].clock);
+       clk_disable_unprepare(crtc->clock);
 
        return 0;
 }