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drm/radeon/ci: disable needless sclk changes
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 18 Nov 2014 20:07:33 +0000 (15:07 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 20 Nov 2014 18:00:13 +0000 (13:00 -0500)
The current code always reprogrammed the sclk levels,
but we don't currently handle disp sclk requirements
so just skip it.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/ci_dpm.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 630434cba22d633e3a0c5635a3141c1d3f702154..3f898d020ae691f9bc38b482fec6a77a05a44843 100644 (file)
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -3809,7 +3809,7 @@ static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
                pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
        } else {
                /* XXX check display min clock requirements */
-               if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
+               if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
                        pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
        }