arm64: dts: m3ulcb: enable SCIF clk and pins

This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 1ae0708bb49503af10b605440c9290d1a4df2d5d..96cda59c2698db3b4348a8a78968f0c4dae748cd 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -37,10 +37,18 @@
 };
 
 &pfc {
+       pinctrl-0 = <&scif_clk_pins>;
+       pinctrl-names = "default";
+
        scif2_pins: scif2 {
                groups = "scif2_data_a";
                function = "scif2";
        };
+
+       scif_clk_pins: scif_clk {
+               groups = "scif_clk_a";
+               function = "scif_clk";
+       };
 };
 
 &scif2 {
@@ -49,3 +57,8 @@
 
        status = "okay";
 };
+
+&scif_clk {
+       clock-frequency = <14745600>;
+       status = "okay";
+};