vpu: txl: add vpu support for txl

PD#168480: vpu: txl: add vpu support for txl

Change-Id: I7562e0831e1f77c65c169c7292ee2a6d2bfc4472
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/common/vpu/vpu.c b/drivers/amlogic/media/common/vpu/vpu.c
index bc5dddf247ab9883f6a9c81b27e50e1ab93506ee..2a10da6e8650fbad05d92b9fd33c59d6bda668f6 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu.c
+++ b/drivers/amlogic/media/common/vpu/vpu.c
@@ -37,7 +37,8 @@
 /* v02: add axg support */
 /* v03: add txlx support */
 /* v04: add g12a support */
-#define VPU_VERION        "v04"
+/* v05: add txl support */
+#define VPU_VERION        "v05"
 
 int vpu_debug_print_flag;
 static spinlock_t vpu_mem_lock;
@@ -1273,6 +1274,28 @@ static struct vpu_data_s vpu_data_gxm = {
        .power_off = vpu_power_off_gx,
 };
 
+static struct vpu_data_s vpu_data_txl = {
+       .chip_type = VPU_CHIP_TXL,
+       .chip_name = "txl",
+       .clk_level_dft = CLK_LEVEL_DFT_TXLX,
+       .clk_level_max = CLK_LEVEL_MAX_TXLX,
+       .fclk_div_table = fclk_div_table_gxb,
+
+       .gp_pll_valid = 0,
+       .mem_pd_reg1_valid = 1,
+       .mem_pd_reg2_valid = 0,
+
+       .mem_pd_table_cnt =
+               sizeof(vpu_mem_pd_txl) / sizeof(struct vpu_ctrl_s),
+       .clk_gate_table_cnt =
+               sizeof(vpu_clk_gate_txl) / sizeof(struct vpu_ctrl_s),
+       .mem_pd_table = vpu_mem_pd_txl,
+       .clk_gate_table = vpu_clk_gate_txl,
+
+       .power_on  = vpu_power_on_txlx,
+       .power_off = vpu_power_off_txlx,
+};
+
 static struct vpu_data_s vpu_data_txlx = {
        .chip_type = VPU_CHIP_TXLX,
        .chip_name = "txlx",
@@ -1378,6 +1401,10 @@ static const struct of_device_id vpu_of_table[] = {
                .compatible = "amlogic, vpu-gxm",
                .data = &vpu_data_gxm,
        },
+       {
+               .compatible = "amlogic, vpu-txl",
+               .data = &vpu_data_txl,
+       },
        {
                .compatible = "amlogic, vpu-txlx",
                .data = &vpu_data_txlx,

diff --git a/drivers/amlogic/media/common/vpu/vpu.h b/drivers/amlogic/media/common/vpu/vpu.h
index 32ca9bb36513d4a3cd5c2e7d57df60c7be06713c..77e494efce3050748e83ce3788fb3d2e2f5dadd5 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu.h
+++ b/drivers/amlogic/media/common/vpu/vpu.h
@@ -30,6 +30,7 @@ enum vpu_chip_e {
        VPU_CHIP_GXTVBB,
        VPU_CHIP_GXL,
        VPU_CHIP_GXM,
+       VPU_CHIP_TXL,
        VPU_CHIP_TXLX,
        VPU_CHIP_AXG,
        VPU_CHIP_G12A,

diff --git a/drivers/amlogic/media/common/vpu/vpu_ctrl.h b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
index 0f099070faea44aabfc37b70d8bc38af48f4c6ed..a38758d44bfb7291b90ea85fffe1d8706a13528f 100644 (file)
--- a/drivers/amlogic/media/common/vpu/vpu_ctrl.h
+++ b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
@@ -193,6 +193,29 @@ static struct vpu_ctrl_s vpu_mem_pd_gxl[] = {
        {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
 };
 
+static struct vpu_ctrl_s vpu_mem_pd_txl[] = {
+       /* vpu module,      reg,                  bit,  len */
+       {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
+       {VPU_VIU_OSD2,      HHI_VPU_MEM_PD_REG0,   2,   2},
+       {VPU_VIU_VD1,       HHI_VPU_MEM_PD_REG0,   4,   2},
+       {VPU_VIU_VD2,       HHI_VPU_MEM_PD_REG0,   6,   2},
+       {VPU_VIU_CHROMA,    HHI_VPU_MEM_PD_REG0,   8,   2},
+       {VPU_VIU_OFIFO,     HHI_VPU_MEM_PD_REG0,  10,   2},
+       {VPU_VIU_SCALE,     HHI_VPU_MEM_PD_REG0,  12,   2},
+       {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0,  14,   2},
+       {VPU_VIU_VDIN0,     HHI_VPU_MEM_PD_REG0,  16,   2},
+       {VPU_VIU_VDIN1,     HHI_VPU_MEM_PD_REG0,  18,   2},
+       {VPU_DI_PRE,        HHI_VPU_MEM_PD_REG0,  26,   2},
+       {VPU_DI_POST,       HHI_VPU_MEM_PD_REG0,  28,   2},
+       {VPU_SHARP,         HHI_VPU_MEM_PD_REG0,  30,   2},
+       {VPU_VPU_ARB,       HHI_VPU_MEM_PD_REG1,  14,   2},
+       {VPU_AFBC_DEC,      HHI_VPU_MEM_PD_REG1,  16,   2},
+       {VPU_VENCP,         HHI_VPU_MEM_PD_REG1,  20,   2},
+       {VPU_VENCL,         HHI_VPU_MEM_PD_REG1,  22,   2},
+       {VPU_VENCI,         HHI_VPU_MEM_PD_REG1,  24,   2},
+       {VPU_MOD_MAX,       VPU_REG_END,           0,   0},
+};
+
 static struct vpu_ctrl_s vpu_mem_pd_txlx[] = {
        /* vpu module,      reg,                  bit,  len */
        {VPU_VIU_OSD1,      HHI_VPU_MEM_PD_REG0,   0,   2},
@@ -393,6 +416,37 @@ static struct vpu_ctrl_s vpu_clk_gate_gxl[] = {
        {VPU_MAX,           VPU_REG_END,           0,   0},
 };
 
+static struct vpu_ctrl_s vpu_clk_gate_txl[] = {
+       /* vpu module,      reg,                  bit,  len */
+       {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */
+       {VPU_VPU_CLKB,      VPU_CLK_GATE,         16,   1},
+       {VPU_RDMA,          VPU_CLK_GATE,         15,   1}, /* rdma_clk */
+       {VPU_VLOCK,         VPU_CLK_GATE,         14,   1},
+       {VPU_MISC,          VPU_CLK_GATE,          6,   1}, /* hs,vs interrupt*/
+       {VPU_VENCP,         VPU_CLK_GATE,          3,   1},
+       {VPU_VENCP,         VPU_CLK_GATE,          0,   1},
+       {VPU_VENCL,         VPU_CLK_GATE,          4,   2},
+       {VPU_VENCI,         VPU_CLK_GATE,         10,   2},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,  24,   6},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   4,  18},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL,   1,   1},
+       {VPU_VIU_VDIN0,     VDIN0_COM_GCLK_CTRL2,  0,   4},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,  24,   6},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   4,  18},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL,   1,   1},
+       {VPU_VIU_VDIN1,     VDIN1_COM_GCLK_CTRL2,  0,   4},
+       {VPU_DI,            DI_CLKG_CTRL,         26,   5},
+       {VPU_DI,            DI_CLKG_CTRL,         24,   1},
+       {VPU_DI,            DI_CLKG_CTRL,         17,   5},
+       {VPU_DI,            DI_CLKG_CTRL,          0,   2},
+       {VPU_VPP,           VPP_GCLK_CTRL0,        2,  30},
+       {VPU_VPP,           VPP_GCLK_CTRL1,        0,  12},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,     18,   8},
+       {VPU_VPP,           VPP_SC_GCLK_CTRL,      2,  10},
+       {VPU_VPP,           VPP_XVYCC_GCLK_CTRL,   0,  18},
+       {VPU_MAX,           VPU_REG_END,           0,   0},
+};
+
 static struct vpu_ctrl_s vpu_clk_gate_txlx[] = {
        /* vpu module,      reg,                  bit,  len */
        {VPU_VPU_TOP,       VPU_CLK_GATE,          1,   1}, /* vpu_system_clk */