KVM: arm64: vgic-v3: Add ICV_CTLR_EL1 handler

Add a handler for reading/writing the guest's view of the ICV_CTLR_EL1
register. only EOIMode and CBPR are of interest here, as all the other
bits directly come from ICH_VTR_EL2 and are Read-Only.

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: David Daney <david.daney@cavium.com>
Acked-by: Christoffer Dall <cdall@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index 406da9c667ffae7d17172c31c2282ae8b70f1e28..a8a58dedc38ee11edae4b81faaf98368ed6fb7ca 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -891,6 +891,46 @@ static void __hyp_text __vgic_v3_read_rpr(struct kvm_vcpu *vcpu,
        vcpu_set_reg(vcpu, rt, val);
 }
 
+static void __hyp_text __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu,
+                                          u32 vmcr, int rt)
+{
+       u32 vtr, val;
+
+       vtr = read_gicreg(ICH_VTR_EL2);
+       /* PRIbits */
+       val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT;
+       /* IDbits */
+       val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT;
+       /* SEIS */
+       val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT;
+       /* A3V */
+       val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT;
+       /* EOImode */
+       val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT;
+       /* CBPR */
+       val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
+
+       vcpu_set_reg(vcpu, rt, val);
+}
+
+static void __hyp_text __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       u32 val = vcpu_get_reg(vcpu, rt);
+
+       if (val & ICC_CTLR_EL1_CBPR_MASK)
+               vmcr |= ICH_VMCR_CBPR_MASK;
+       else
+               vmcr &= ~ICH_VMCR_CBPR_MASK;
+
+       if (val & ICC_CTLR_EL1_EOImode_MASK)
+               vmcr |= ICH_VMCR_EOIM_MASK;
+       else
+               vmcr &= ~ICH_VMCR_EOIM_MASK;
+
+       write_gicreg(vmcr, ICH_VMCR_EL2);
+}
+
 int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
 {
        int rt;
@@ -983,6 +1023,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
        case SYS_ICC_RPR_EL1:
                fn = __vgic_v3_read_rpr;
                break;
+       case SYS_ICC_CTLR_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_ctlr;
+               else
+                       fn = __vgic_v3_write_ctlr;
+               break;
        default:
                return 0;
        }