drm/radeon: take ownership of pipe initialization

Take ownership of pipe initialization away from KFD.

Note that hpd_eop_gpu_addr was already large enough to accomodate all
pipes.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 008c145b7f29f60a298419931f1922555de5e35a..09504b14f514cfb44856192dde4ec0b9bc1baf52 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4580,23 +4580,24 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
        /* init the pipes */
        mutex_lock(&rdev->srbm_mutex);
 
-       eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr;
+       for (i = 0; i < rdev->mec.num_pipe; ++i) {
+               cik_srbm_select(rdev, 0, i, 0, 0);
 
-       cik_srbm_select(rdev, 0, 0, 0, 0);
-
-       /* write the EOP addr */
-       WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
-       WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
+               eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ;
+               /* write the EOP addr */
+               WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
+               WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
 
-       /* set the VMID assigned */
-       WREG32(CP_HPD_EOP_VMID, 0);
+               /* set the VMID assigned */
+               WREG32(CP_HPD_EOP_VMID, 0);
 
-       /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
-       tmp = RREG32(CP_HPD_EOP_CONTROL);
-       tmp &= ~EOP_SIZE_MASK;
-       tmp |= order_base_2(MEC_HPD_SIZE / 8);
-       WREG32(CP_HPD_EOP_CONTROL, tmp);
+               /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
+               tmp = RREG32(CP_HPD_EOP_CONTROL);
+               tmp &= ~EOP_SIZE_MASK;
+               tmp |= order_base_2(MEC_HPD_SIZE / 8);
+               WREG32(CP_HPD_EOP_CONTROL, tmp);
 
+       }
        mutex_unlock(&rdev->srbm_mutex);
 
        /* init the queues.  Just two for now. */

diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c
index 87a9ebb5f58f3befe0e8c1fc697cfcdce09bd078..a06e3b130b9e1a8e150ae833e27c5cd19e1a1a65 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_kfd.c
+++ b/drivers/gpu/drm/radeon/radeon_kfd.c
@@ -423,18 +423,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
                                uint32_t hpd_size, uint64_t hpd_gpu_addr)
 {
-       uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
-       uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
-
-       lock_srbm(kgd, mec, pipe, 0, 0);
-       write_register(kgd, CP_HPD_EOP_BASE_ADDR,
-                       lower_32_bits(hpd_gpu_addr >> 8));
-       write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
-                       upper_32_bits(hpd_gpu_addr >> 8));
-       write_register(kgd, CP_HPD_EOP_VMID, 0);
-       write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
-       unlock_srbm(kgd);
-
+       /* nothing to do here */
        return 0;
 }