ARM: dts: dra72x-evm: Enable CPSW and MDIO

Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 812f7b44c7509269d13cb58e59c6737a445c4091..abbaaa782f88092444d91d30579e5c5f949d9b45 100644 (file)
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -365,3 +365,76 @@
        bus-width = <8>;
        ti,non-removable;
 };
+
+&dra7_pmx_core {
+       cpsw_default: cpsw_default {
+               pinctrl-single,pins = <
+                       /* Slave 2 */
+                       0x198 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d12.rgmii1_txc */
+                       0x19c (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d13.rgmii1_tctl */
+                       0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d14.rgmii1_td3 */
+                       0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d15.rgmii1_td2 */
+                       0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d16.rgmii1_td1 */
+                       0x1ac (PIN_OUTPUT | MUX_MODE3)  /* vin2a_d17.rgmii1_td0 */
+                       0x1b0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d18.rgmii1_rclk */
+                       0x1b4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d19.rgmii1_rctl */
+                       0x1b8 (PIN_INPUT | MUX_MODE3)   /* vin2a_d20.rgmii1_rd3 */
+                       0x1bc (PIN_INPUT | MUX_MODE3)   /* vin2a_d21.rgmii1_rd2 */
+                       0x1c0 (PIN_INPUT | MUX_MODE3)   /* vin2a_d22.rgmii1_rd1 */
+                       0x1c4 (PIN_INPUT | MUX_MODE3)   /* vin2a_d23.rgmii1_rd0 */
+               >;
+
+       };
+
+       cpsw_sleep: cpsw_sleep {
+               pinctrl-single,pins = <
+                       /* Slave 2 */
+                       0x198 (MUX_MODE15)
+                       0x19c (MUX_MODE15)
+                       0x1a0 (MUX_MODE15)
+                       0x1a4 (MUX_MODE15)
+                       0x1a8 (MUX_MODE15)
+                       0x1ac (MUX_MODE15)
+                       0x1b0 (MUX_MODE15)
+                       0x1b4 (MUX_MODE15)
+                       0x1b8 (MUX_MODE15)
+                       0x1bc (MUX_MODE15)
+                       0x1c0 (MUX_MODE15)
+                       0x1c4 (MUX_MODE15)
+               >;
+       };
+
+       davinci_mdio_default: davinci_mdio_default {
+               pinctrl-single,pins = <
+                       /* MDIO */
+                       0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_d.mdio_d */
+                       0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk.mdio_clk */
+               >;
+       };
+
+       davinci_mdio_sleep: davinci_mdio_sleep {
+               pinctrl-single,pins = <
+                       0x23c (MUX_MODE15)
+                       0x240 (MUX_MODE15)
+               >;
+       };
+};
+
+&mac {
+       status = "okay";
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&cpsw_default>;
+       pinctrl-1 = <&cpsw_sleep>;
+};
+
+&cpsw_emac1 {
+       phy_id = <&davinci_mdio>, <3>;
+       phy-mode = "rgmii";
+};
+
+&davinci_mdio {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&davinci_mdio_default>;
+       pinctrl-1 = <&davinci_mdio_sleep>;
+       active_slave = <1>;
+};