net: stmmac: mapping mtl rx to dma channel
authorJoao Pinto <Joao.Pinto@synopsys.com>
Fri, 10 Mar 2017 18:24:55 +0000 (18:24 +0000)
committerDavid S. Miller <davem@davemloft.net>
Mon, 13 Mar 2017 06:41:03 +0000 (23:41 -0700)
This patch adds the functionality of RX queue to dma channel mapping
based on configuration.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/common.h
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

index f61611c8e8b0602a17712c495262e3b2c60df94e..7d23e3dc7797686cfa57b092b9798ac2f24485c0 100644 (file)
@@ -465,6 +465,8 @@ struct stmmac_ops {
        /* Set MTL TX queues weight */
        void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
                                        u32 weight, u32 queue);
+       /* RX MTL queue to RX dma mapping */
+       void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
        /* Dump MAC registers */
        void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
        /* Handle extra events on specific interrupts hw dependent */
index 89824fe484f6485f2ee2213e563dea7e2c091159..773f25b8e40399b3e3ed53c502150de475330e68 100644 (file)
@@ -177,6 +177,13 @@ enum power_event {
 #define MTL_INT_STATUS                 0x00000c20
 #define MTL_INT_Q0                     BIT(0)
 
+#define MTL_RXQ_DMA_MAP0               0x00000c30 /* queue 0 to 3 */
+#define MTL_RXQ_DMA_MAP1               0x00000c34 /* queue 4 to 7 */
+#define MTL_RXQ_DMA_Q04MDMACH_MASK     GENMASK(3, 0)
+#define MTL_RXQ_DMA_Q04MDMACH(x)       ((x) << 0)
+#define MTL_RXQ_DMA_QXMDMACH_MASK(x)   GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
+#define MTL_RXQ_DMA_QXMDMACH(chan, q)  ((chan) << (8 * (q)))
+
 #define MTL_CHAN_BASE_ADDR             0x00000d00
 #define MTL_CHAN_BASE_OFFSET           0x40
 #define MTL_CHANX_BASE_ADDR(x)         (MTL_CHAN_BASE_ADDR + \
index 21a696eda9ce0687fd35e5c91110b0faff0ae0d4..e9b153f75538970060871288bff38b885f4938a3 100644 (file)
@@ -131,6 +131,30 @@ static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
        writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 }
 
+static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
+{
+       void __iomem *ioaddr = hw->pcsr;
+       u32 value;
+
+       if (queue < 4)
+               value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
+       else
+               value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
+
+       if (queue == 0 || queue == 4) {
+               value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
+               value |= MTL_RXQ_DMA_Q04MDMACH(chan);
+       } else {
+               value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
+               value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
+       }
+
+       if (queue < 4)
+               writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
+       else
+               writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
+}
+
 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 {
        void __iomem *ioaddr = hw->pcsr;
@@ -521,6 +545,7 @@ static const struct stmmac_ops dwmac4_ops = {
        .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
        .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
        .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
+       .map_mtl_to_dma = dwmac4_map_mtl_dma,
        .dump_regs = dwmac4_dump_regs,
        .host_irq_status = dwmac4_irq_status,
        .flow_ctrl = dwmac4_flow_ctrl,
index 43036dabb9f9d528736c67e0e21be4ff92aac1b3..e1d5fe7f54a9097e7d7d84b12f2cc3f7888de469 100644 (file)
@@ -1659,6 +1659,23 @@ static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
        }
 }
 
+/**
+ *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
+ *  @priv: driver private structure
+ *  Description: It is used for mapping RX queues to RX dma channels
+ */
+static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
+{
+       u32 rx_queues_count = priv->plat->rx_queues_to_use;
+       u32 queue;
+       u32 chan;
+
+       for (queue = 0; queue < rx_queues_count; queue++) {
+               chan = priv->plat->rx_queues_cfg[queue].chan;
+               priv->hw->mac->map_mtl_to_dma(priv->hw, queue, chan);
+       }
+}
+
 /**
  *  stmmac_mtl_configuration - Configure MTL
  *  @priv: driver private structure
@@ -1682,6 +1699,10 @@ static void stmmac_mtl_configuration(struct stmmac_priv *priv)
                priv->hw->mac->prog_mtl_tx_algorithms(priv->hw,
                                                priv->plat->tx_sched_algorithm);
 
+       /* Map RX MTL to DMA channels */
+       if (rx_queues_count > 1 && priv->hw->mac->map_mtl_to_dma)
+               stmmac_rx_queue_dma_chan_map(priv);
+
        /* Enable MAC RX Queues */
        if (rx_queues_count > 1 && priv->hw->mac->rx_queue_enable)
                stmmac_mac_enable_rx_queues(priv);