ARM: EXYNOS: Add generic cpu power control functions for exynos SoCs
authorLeela Krishna Amudala <leela.krishna@linaro.org>
Thu, 15 May 2014 19:23:24 +0000 (04:23 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Thu, 15 May 2014 19:24:24 +0000 (04:24 +0900)
Add generic cpu power control functions for exynos based
SoCS for cpu power up/down and to know the cpu status.

Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-exynos/common.h
arch/arm/mach-exynos/pm.c
arch/arm/mach-exynos/regs-pmu.h

index 963c51fb606c520a17df85b75621b5d6b2e15ea0..4d815a511bc11277a464165985568659766ae0d0 100644 (file)
@@ -63,5 +63,8 @@ struct exynos_pmu_conf {
 };
 
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_cpu_power_down(int cpu);
+extern void exynos_cpu_power_up(int cpu);
+extern int  exynos_cpu_power_state(int cpu);
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
index 15af0ceb0a66a063d0c2ed948ca4a28a1109c777..cbfe23598236fb7f6929fe5e23b5f5e9745a1df7 100644 (file)
@@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
        return -ENOENT;
 }
 
+/**
+ * exynos_core_power_down : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power down the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_power_down(int cpu)
+{
+       __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_up : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_power_up(int cpu)
+{
+       __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                    EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+       return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+                       S5P_CORE_LOCAL_PWR_EN);
+}
+
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
 
index 4f6a2560d0220e0244eb35d55f1ebc55e66cc734..84634ac5b1274f331e2ba3619c477aa394f005a6 100644 (file)
 #define S5P_GPS_LOWPWR                         S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR                   S5P_PMUREG(0x13A0)
 
+#define EXYNOS_ARM_CORE0_CONFIGURATION         S5P_PMUREG(0x2000)
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)     \
+                       (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_ARM_CORE_STATUS(_nr)            \
+                       (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+
 #define S5P_ARM_CORE1_CONFIGURATION            S5P_PMUREG(0x2080)
 #define S5P_ARM_CORE1_STATUS                   S5P_PMUREG(0x2084)