MIPS: FRE: Use set/clear_c0_config5 instead of open coded sequences.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 5528f4e2af6a72f882e1d839039d441adb25ae92..affebb78f5d6573dbf97f62630ad1e6a35026602 100644 (file)
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -64,7 +64,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
                        return SIGFPE;
 
                /* set FRE */
-               write_c0_config5(read_c0_config5() | MIPS_CONF5_FRE);
+               set_c0_config5(MIPS_CONF5_FRE);
                goto fr_common;
 
        case FPU_64BIT:
@@ -76,7 +76,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
        case FPU_32BIT:
                if (cpu_has_fre) {
                        /* clear FRE */
-                       write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
+                       clear_c0_config5(MIPS_CONF5_FRE);
                }
 fr_common:
                /* set CU1 & change FR appropriately */
@@ -196,15 +196,13 @@ static inline int init_fpu(void)
                        return 0;
                }
 
-               config5 = read_c0_config5();
-
                /*
                 * Ensure FRE is clear whilst running _init_fpu, since
                 * single precision FP instructions are used. If FRE
                 * was set then we'll just end up initialising all 32
                 * 64b registers.
                 */
-               write_c0_config5(config5 & ~MIPS_CONF5_FRE);
+               config5 = clear_c0_config5(MIPS_CONF5_FRE);
                enable_fpu_hazard();
 
                _init_fpu();