powerpc/perf: fix fsl_emb_pmu_start to write correct pmc value

PMCs on PowerPC increases towards 0x80000000 and triggers an overflow
interrupt when the msb is set to collect a sample. Therefore, to setup
for the next sample collection, pmu_start should set the pmc value to
0x80000000 - left instead of left which incorrectly delays the next
overflow interrupt. Same as commit 9a45a9407c69 ("powerpc/perf:
power_pmu_start restores incorrect values, breaking frequency events")
for book3s.

Signed-off-by: Tom Huynh <tom.huynh@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 4acaea01fe0313f99a69efa1331a2fbf158f001d..e9fe904b653804e33ec15a0a71f2510a5431f62e 100644 (file)
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -389,6 +389,7 @@ static void fsl_emb_pmu_del(struct perf_event *event, int flags)
 static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags)
 {
        unsigned long flags;
+       unsigned long val;
        s64 left;
 
        if (event->hw.idx < 0 || !event->hw.sample_period)
@@ -405,7 +406,10 @@ static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags)
 
        event->hw.state = 0;
        left = local64_read(&event->hw.period_left);
-       write_pmc(event->hw.idx, left);
+       val = 0;
+       if (left < 0x80000000L)
+               val = 0x80000000L - left;
+       write_pmc(event->hw.idx, val);
 
        perf_event_update_userpage(event);
        perf_pmu_enable(event->pmu);