arm64: dts: marvell: update Armada AP806 clock description

Following the review from the DT maintainers, the DT binding for the
clocks has changed, and we now use a DFX server node exposing a
syscon, with the clock nodes being subnodes of the DFX server
node. This commit therefore updates the AP806 Device Tree file to use
this new DT binding.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 63f25ce76d3334f1471f343355f50a4668d4e5b4..88e334830b777fc55d6eab34cd52477245c86e0a 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -179,23 +179,6 @@
 
                        };
 
-                       coreclk: clk@0x6F8204 {
-                               compatible = "marvell,armada-ap806-core-clock";
-                               reg = <0x6F8204 0x04>;
-                               #clock-cells = <1>;
-                               clock-output-names = "ddr", "ring", "cpu";
-                       };
-
-                       ringclk: clk@0x6F8250 {
-                               compatible = "marvell,armada-ap806-ring-clock";
-                               reg = <0x6F8250 0x04>;
-                               #clock-cells = <1>;
-                               clock-output-names = "ring-0", "ring-2",
-                                                    "ring-3", "ring-4",
-                                                    "ring-5";
-                               clocks = <&coreclk 1>;
-                       };
-
                        xor0@400000 {
                                compatible = "marvell,mv-xor-v2";
                                reg = <0x400000 0x1000>,
@@ -227,6 +210,26 @@
                                msi-parent = <&gic_v2m0>;
                                dma-coherent;
                        };
+
+                       dfx-server@6f8000 {
+                               compatible = "simple-mfd", "syscon";
+                               reg = <0x6f8000 0x70000>;
+
+                               coreclk: clk@204 {
+                                       compatible = "marvell,armada-ap806-core-clock";
+                                       #clock-cells = <1>;
+                                       clock-output-names = "ddr", "ring", "cpu";
+                               };
+
+                               ringclk: clk@250 {
+                                       compatible = "marvell,armada-ap806-ring-clock";
+                                       #clock-cells = <1>;
+                                       clock-output-names = "ring-0", "ring-2",
+                                                            "ring-3", "ring-4",
+                                                            "ring-5";
+                                       clocks = <&coreclk 1>;
+                               };
+                       };
                };
        };