MIPS: c-r4k: Drop bc_wback_inv() from icache flush

The EVA conditional bc_wback_inv() at the end of flush_icache_range() to
flush the modified code all the way back to RAM was apparently there for
debug purposes and to accommodate the Malta EVA configuration which
makes use of a physical alias, and didn't use the CP0_EBase.WG (Write
Gate) bit to put the exception vector in the same physical alias where
the exception vector code is written and is being flushed.

Now that CP0_EBase.WG is used, lets drop this flush.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fa7d8d3790bfc960bc7d4b358e9fb1a5120c04e2..bbb7dfea40f9f4c61555a6df42600bb1a392308d 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -752,17 +752,6 @@ static inline void __local_r4k_flush_icache_range(unsigned long start,
                        break;
                }
        }
-#ifdef CONFIG_EVA
-       /*
-        * Due to all possible segment mappings, there might cache aliases
-        * caused by the bootloader being in non-EVA mode, and the CPU switching
-        * to EVA during early kernel init. It's best to flush the scache
-        * to avoid having secondary cores fetching stale data and lead to
-        * kernel crashes.
-        */
-       bc_wback_inv(start, (end - start));
-       __sync();
-#endif
 }
 
 static inline void local_r4k_flush_icache_range(unsigned long start,