* Some useless abstractions
*/
#define chan_to_DAC(a) ((a)&1)
-#define update_dacsr(a) outw(devpriv->dacsr|(a), dev->iobase+DT2821_DACSR)
-#define update_adcsr(a) outw(devpriv->adcsr|(a), dev->iobase+DT2821_ADCSR)
#define mux_busy() (inw(dev->iobase+DT2821_ADCSR)&DT2821_MUXBUSY)
#define ad_done() (inw(dev->iobase+DT2821_ADCSR)&DT2821_ADDONE)
-#define update_supcsr(a) outw(devpriv->supcsr|(a), dev->iobase+DT2821_SUPCSR)
/*
* danger! macro abuse... a is the expression to wait on, and b is
int i;
struct comedi_subdevice *s = dev->subdevices + 1;
- update_supcsr(DT2821_CLRDMADNE);
+ outw(devpriv->supcsr | DT2821_CLRDMADNE, dev->iobase + DT2821_SUPCSR);
if (!s->async->prealloc_buf) {
printk(KERN_ERR "async->data disappeared. dang!\n");
int ret;
struct comedi_subdevice *s = dev->subdevices;
- update_supcsr(DT2821_CLRDMADNE);
+ outw(devpriv->supcsr | DT2821_CLRDMADNE, dev->iobase + DT2821_SUPCSR);
if (!s->async->prealloc_buf) {
printk(KERN_ERR "async->data disappeared. dang!\n");
/* XXX probably wrong */
if (!devpriv->ntrig) {
devpriv->supcsr &= ~(DT2821_DDMA);
- update_supcsr(0);
+ outw(devpriv->supcsr, dev->iobase + DT2821_SUPCSR);
}
#endif
/* restart the channel */
s->async->events |= COMEDI_CB_EOA;
} else {
if (supcsr & DT2821_SCDN)
- update_supcsr(DT2821_STRIG);
+ outw(devpriv->supcsr | DT2821_STRIG,
+ dev->iobase + DT2821_SUPCSR);
}
handled = 1;
}
for (i = 0; i < n; i++) {
chan = CR_CHAN(chanlist[i]);
range = CR_RANGE(chanlist[i]);
- update_adcsr((range << 4) | (chan));
+ outw(devpriv->adcsr | (range << 4) | chan,
+ dev->iobase + DT2821_ADCSR);
}
outw(n - 1, dev->iobase + DT2821_CHANCSR);
}
/* XXX should we really be enabling the ad clock here? */
devpriv->adcsr = DT2821_ADCLK;
- update_adcsr(0);
+ outw(devpriv->adcsr, dev->iobase + DT2821_ADCSR);
dt282x_load_changain(dev, 1, &insn->chanspec);
- update_supcsr(DT2821_PRLD);
+ outw(devpriv->supcsr | DT2821_PRLD, dev->iobase + DT2821_SUPCSR);
wait_for(!mux_busy(), comedi_error(dev, "timeout\n"); return -ETIME;);
for (i = 0; i < insn->n; i++) {
- update_supcsr(DT2821_STRIG);
+ outw(devpriv->supcsr | DT2821_STRIG,
+ dev->iobase + DT2821_SUPCSR);
wait_for(ad_done(), comedi_error(dev, "timeout\n");
return -ETIME;);
/* external trigger */
devpriv->supcsr = DT2821_ERRINTEN | DT2821_DS0 | DT2821_DS1;
}
- update_supcsr(DT2821_CLRDMADNE | DT2821_BUFFB | DT2821_ADCINIT);
+ outw(devpriv->supcsr | DT2821_CLRDMADNE | DT2821_BUFFB | DT2821_ADCINIT,
+ dev->iobase + DT2821_SUPCSR);
devpriv->ntrig = cmd->stop_arg * cmd->scan_end_arg;
devpriv->nread = devpriv->ntrig;
if (devpriv->ntrig) {
prep_ai_dma(dev, 1, 0);
devpriv->supcsr |= DT2821_DDMA;
- update_supcsr(0);
+ outw(devpriv->supcsr, dev->iobase + DT2821_SUPCSR);
}
devpriv->adcsr = 0;
dt282x_load_changain(dev, cmd->chanlist_len, cmd->chanlist);
devpriv->adcsr = DT2821_ADCLK | DT2821_IADDONE;
- update_adcsr(0);
+ outw(devpriv->adcsr, dev->iobase + DT2821_ADCSR);
- update_supcsr(DT2821_PRLD);
+ outw(devpriv->supcsr | DT2821_PRLD, dev->iobase + DT2821_SUPCSR);
wait_for(!mux_busy(), comedi_error(dev, "timeout\n"); return -ETIME;);
if (cmd->scan_begin_src == TRIG_FOLLOW) {
- update_supcsr(DT2821_STRIG);
+ outw(devpriv->supcsr | DT2821_STRIG,
+ dev->iobase + DT2821_SUPCSR);
} else {
devpriv->supcsr |= DT2821_XTRIG;
- update_supcsr(0);
+ outw(devpriv->supcsr, dev->iobase + DT2821_SUPCSR);
}
return 0;
dt282x_disable_dma(dev);
devpriv->adcsr = 0;
- update_adcsr(0);
+ outw(devpriv->adcsr, dev->iobase + DT2821_ADCSR);
devpriv->supcsr = 0;
- update_supcsr(DT2821_ADCINIT);
+ outw(devpriv->supcsr | DT2821_ADCINIT, dev->iobase + DT2821_SUPCSR);
return 0;
}
d ^= (1 << (boardtype.dabits - 1));
}
- update_dacsr(0);
+ outw(devpriv->dacsr, dev->iobase + DT2821_DACSR);
outw(d, dev->iobase + DT2821_DADAT);
- update_supcsr(DT2821_DACON);
+ outw(devpriv->supcsr | DT2821_DACON, dev->iobase + DT2821_SUPCSR);
return 1;
}
}
prep_ao_dma(dev, 1, size);
- update_supcsr(DT2821_STRIG);
+ outw(devpriv->supcsr | DT2821_STRIG, dev->iobase + DT2821_SUPCSR);
s->async->inttrig = NULL;
return 1;
dt282x_disable_dma(dev);
devpriv->supcsr = DT2821_ERRINTEN | DT2821_DS1 | DT2821_DDMA;
- update_supcsr(DT2821_CLRDMADNE | DT2821_BUFFB | DT2821_DACINIT);
+ outw(devpriv->supcsr | DT2821_CLRDMADNE | DT2821_BUFFB | DT2821_DACINIT,
+ dev->iobase + DT2821_SUPCSR);
devpriv->ntrig = cmd->stop_arg * cmd->chanlist_len;
devpriv->nread = devpriv->ntrig;
outw(timer, dev->iobase + DT2821_TMRCTR);
devpriv->dacsr = DT2821_SSEL | DT2821_DACLK | DT2821_IDARDY;
- update_dacsr(0);
+ outw(devpriv->dacsr, dev->iobase + DT2821_DACSR);
s->async->inttrig = dt282x_ao_inttrig;
dt282x_disable_dma(dev);
devpriv->dacsr = 0;
- update_dacsr(0);
+ outw(devpriv->dacsr, dev->iobase + DT2821_DACSR);
devpriv->supcsr = 0;
- update_supcsr(DT2821_DACINIT);
+ outw(devpriv->supcsr | DT2821_DACINIT, dev->iobase + DT2821_SUPCSR);
return 0;
}