ARM: dts: DRA7: Add pcie1 dt node for EP mode

Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index adc70fb091a21d5cb772996daade83e470f1bfa9..0c0bb4e93f25b91d893a5e3c74165f040dd3000a 100644 (file)
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -96,3 +96,12 @@
                status = "okay";
        };
 };
+
+&pcie1_rc {
+       status = "okay";
+       gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
+       gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};

diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index cb263222522088ee4bed681a462750cfd5483042..604d52554eda773ab770293b02734a7f3a95a3c4 100644 (file)
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -88,7 +88,12 @@
        load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
 };
 
-&pcie1 {
+&pcie1_rc {
+       status = "okay";
+       gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+};
+
+&pcie1_ep {
        gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
 };
 

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index fdfe5b16b806298a1aac3a136a873dfc2ab891df..d433a50cd18aac1e4dc37c9aa0efe78e9e18e6e6 100644 (file)
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -570,7 +570,12 @@
        };
 };
 
-&pcie1 {
+&pcie1_rc {
+       status = "ok";
+       gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&pcie1_ep {
        gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
 };
 

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ee04d8d7abab28facee3df7a686d8a79013b49c4..41539b75046cb69bfdca3008d5b25e10614051d9 100644 (file)
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -729,3 +729,7 @@
                status = "okay";
        };
 };
+
+&pcie1_rc {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 32347d7f00d7c935718399227fbe59d117a6e32f..02a136a4661aa1ed172e4926a7a8dabad9e271b9 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -196,6 +196,7 @@
                                scm_conf1: scm_conf@1c04 {
                                        compatible = "syscon";
                                        reg = <0x1c04 0x0020>;
+                                       #syscon-cells = <2>;
                                };
 
                                scm_conf_pcie: scm_conf@1c24 {
@@ -287,7 +288,11 @@
                        #address-cells = <1>;
                        ranges = <0x51000000 0x51000000 0x3000
                                  0x0        0x20000000 0x10000000>;
-                       pcie1: pcie@51000000 {
+                       /**
+                        * To enable PCI endpoint mode, disable the pcie1_rc
+                        * node and enable pcie1_ep mode.
+                        */
+                       pcie1_rc: pcie@51000000 {
                                compatible = "ti,dra7-pcie";
                                reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
                                reg-names = "rc_dbics", "ti_conf", "config";
@@ -309,12 +314,28 @@
                                                <0 0 0 2 &pcie1_intc 2>,
                                                <0 0 0 3 &pcie1_intc 3>,
                                                <0 0 0 4 &pcie1_intc 4>;
+                               status = "disabled";
                                pcie1_intc: interrupt-controller {
                                        interrupt-controller;
                                        #address-cells = <0>;
                                        #interrupt-cells = <1>;
                                };
                        };
+
+                       pcie1_ep: pcie_ep@51000000 {
+                               compatible = "ti,dra7-pcie-ep";
+                               reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
+                               reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
+                               interrupts = <0 232 0x4>;
+                               num-lanes = <1>;
+                               num-ib-windows = <4>;
+                               num-ob-windows = <16>;
+                               ti,hwmods = "pcie1";
+                               phys = <&pcie1_phy>;
+                               phy-names = "pcie-phy0";
+                               ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+                               status = "disabled";
+                       };
                };
 
                axi@1 {

diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 05d5408394340f63f08acac63ed6fde0a67958c8..2e485a13dfd7e1fe470f071022ac4332e1445ea1 100644 (file)
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -563,3 +563,7 @@
                status = "okay";
        };
 };
+
+&pcie1_rc {
+       status = "okay";
+};