if (sz <= 0)
return -EIO;
}
+
+ /*
+ * The CPU firmware apparently sets up to receive an interrupt for it's
+ * outgoing IRQ_CPU_TO_EPU_ACK to us (*boggle*). We get an interrupt
+ * when it sends us an ack, but by the time we process it, that flag in
+ * the SW2 status register has been cleared by the CPU firmware.
+ * We'll prevent that not so useful behavior by clearing the CPU's
+ * interrupt enables for Ack IRQ's we want to process.
+ */
+ cx18_sw2_irq_disable_cpu(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
+
/* initialize GPIO */
cx18_write_reg_expect(cx, 0x14001400, 0xc78110, 0x00001400, 0x14001400);
return 0;
cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI);
}
+void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
+{
+ u32 r;
+ r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
+ cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
+}
+
void cx18_setup_page(struct cx18 *cx, u32 addr)
{
u32 val;
void cx18_sw1_irq_disable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_enable(struct cx18 *cx, u32 val);
void cx18_sw2_irq_disable(struct cx18 *cx, u32 val);
+void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val);
void cx18_setup_page(struct cx18 *cx, u32 addr);
#endif /* CX18_IO_H */
#define SW1_INT_ENABLE_PCI 0xc7311c
#define SW2_INT_SET 0xc73140
#define SW2_INT_STATUS 0xc73144
+#define SW2_INT_ENABLE_CPU 0xc73158
#define SW2_INT_ENABLE_PCI 0xc7315c
irqreturn_t cx18_irq_handler(int irq, void *dev_id);