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ARM: pxa910: correct nand pmu setting
author
Lei Wen
<leiwen@marvell.com>
Tue, 21 Jun 2011 09:54:18 +0000
(
02:54
-0700)
committer
Eric Miao
<eric.y.miao@gmail.com>
Wed, 6 Jul 2011 15:51:22 +0000
(23:51 +0800)
The original pair of <0x01db,
208000000
> is invalid.
Correct to the valid value.
Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: stable@kernel.org
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
arch/arm/mach-mmp/pxa910.c
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diff --git
a/arch/arm/mach-mmp/pxa910.c
b/arch/arm/mach-mmp/pxa910.c
index 8f92ccd26edf9f77457d34f7429fb9182dd5e62d..1464607aa60db76632ce72b0008cfa4333178b13 100644
(file)
--- a/
arch/arm/mach-mmp/pxa910.c
+++ b/
arch/arm/mach-mmp/pxa910.c
@@
-110,7
+110,7
@@
static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APMU_CLK(nand, NAND, 0x
01db, 208
000000);
+static APMU_CLK(nand, NAND, 0x
19b, 156
000000);
static APMU_CLK(u2o, USB, 0x1b, 480000000);
/* device and clock bindings */