void __iomem *base;
int irq;
+ void (*dsi_mux_pads)(bool enable);
+
struct dsi_clock_info current_cinfo;
bool vdds_dsi_enabled;
DSSDBGF();
+ if (dsi.dsi_mux_pads)
+ dsi.dsi_mux_pads(true);
+
dsi_enable_scp_clk();
/* A dummy read using the SCP interface to any DSIPHY register is
dsi_cio_disable_lane_override();
err_scp_clk_dom:
dsi_disable_scp_clk();
+ if (dsi.dsi_mux_pads)
+ dsi.dsi_mux_pads(false);
return r;
}
{
dsi_cio_power(DSI_COMPLEXIO_POWER_OFF);
dsi_disable_scp_clk();
+ if (dsi.dsi_mux_pads)
+ dsi.dsi_mux_pads(false);
}
static int _dsi_wait_reset(void)
static int dsi_init(struct platform_device *pdev)
{
+ struct omap_display_platform_data *dss_plat_data;
+ struct omap_dss_board_info *board_info;
u32 rev;
int r, i;
struct resource *dsi_mem;
+ dss_plat_data = pdev->dev.platform_data;
+ board_info = dss_plat_data->board_data;
+ dsi.dsi_mux_pads = board_info->dsi_mux_pads;
+
spin_lock_init(&dsi.irq_lock);
spin_lock_init(&dsi.errors_lock);
dsi.errors = 0;
int num_devices;
struct omap_dss_device **devices;
struct omap_dss_device *default_device;
+ void (*dsi_mux_pads)(bool enable);
};
#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)