MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()
authorEunbong Song <eunb.song@samsung.com>
Fri, 11 Apr 2014 08:32:54 +0000 (08:32 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 28 May 2014 09:03:39 +0000 (11:03 +0200)
In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality
fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type"
message. This patch solve this problem.

Signed-off-by: Eunbong Song <eunb.song@samsung.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6747/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pci/msi-octeon.c

index 2b91b0e6156670a723c4cd46749065a0f798d347..ab0c5d14c6f7289ac52554976ab7da9130cf4b41 100644 (file)
@@ -15,6 +15,7 @@
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
 #include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
 #include <asm/octeon/pci-octeon.h>
 
@@ -162,6 +163,11 @@ msi_irq_allocated:
                msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
                msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
                break;
+       case OCTEON_DMA_BAR_TYPE_PCIE2:
+               /* When using PCIe2, Bar 0 is based at 0 */
+               msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
+               msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
+               break;
        default:
                panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
        }