drm/amdgpu/gfx8: move MEC doorbell range setting

It's global, not queue specific, so move it out of the
kiq register init function.

Tested-and-Reviewed-by:  Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5e317675ab623725eb8a8ccc9ade05dea3258103..818b07b40910f877b6384a30e761f57ac83822ea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4942,20 +4942,6 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring)
        WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
        WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, mqd->cp_hqd_pq_wptr_poll_addr_hi);
 
-       /* enable the doorbell if requested */
-       if (ring->use_doorbell) {
-               if ((adev->asic_type == CHIP_CARRIZO) ||
-                   (adev->asic_type == CHIP_FIJI) ||
-                   (adev->asic_type == CHIP_STONEY) ||
-                   (adev->asic_type == CHIP_POLARIS10) ||
-                   (adev->asic_type == CHIP_POLARIS11) ||
-                   (adev->asic_type == CHIP_POLARIS12)) {
-                       WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
-                                               AMDGPU_DOORBELL_KIQ << 2);
-                       WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-                                               AMDGPU_DOORBELL_MEC_RING7 << 2);
-               }
-       }
        WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, mqd->cp_hqd_pq_doorbell_control);
 
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
@@ -5082,6 +5068,18 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
                        goto done;
        }
 
+       if ((adev->asic_type == CHIP_CARRIZO) ||
+           (adev->asic_type == CHIP_FIJI) ||
+           (adev->asic_type == CHIP_STONEY) ||
+           (adev->asic_type == CHIP_POLARIS10) ||
+           (adev->asic_type == CHIP_POLARIS11) ||
+           (adev->asic_type == CHIP_POLARIS12)) {
+               WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
+                      AMDGPU_DOORBELL_KIQ << 2);
+               WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
+                      AMDGPU_DOORBELL_MEC_RING7 << 2);
+       }
+
        r = gfx_v8_0_kiq_kcq_enable(adev);
        if (r)
                goto done;