drm/vc4: Set up SCALER_DISPCTRL at boot.

We want the HVS on, obviously, and we also want DSP3 (PV1's source) to
be muxed from HVS channel 2 like we expect in vc4_crtc.c.  The
firmware wasn't setting the DSP3 mux up when both the LCD and HDMI
were disabled.

Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/20161214194621.16499-5-eric@anholt.net

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 6fbab1c82cb1089bde0834f3e0bf1fdf99f54221..fc68b1b4da5249ce3181d7eabb0a08bf8e4908cf 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -170,6 +170,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
        struct vc4_dev *vc4 = drm->dev_private;
        struct vc4_hvs *hvs = NULL;
        int ret;
+       u32 dispctrl;
 
        hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
        if (!hvs)
@@ -211,6 +212,19 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
                return ret;
 
        vc4->hvs = hvs;
+
+       dispctrl = HVS_READ(SCALER_DISPCTRL);
+
+       dispctrl |= SCALER_DISPCTRL_ENABLE;
+
+       /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
+        * be unused.
+        */
+       dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
+       dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
+
+       HVS_WRITE(SCALER_DISPCTRL, dispctrl);
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 39f6886b24100c43b590e47e0c7bc44846721d65..b3b297fba7097bc495fa8916292c547925720199 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -244,6 +244,9 @@
 # define SCALER_DISPCTRL_ENABLE                        BIT(31)
 # define SCALER_DISPCTRL_DSP2EISLUR            BIT(15)
 # define SCALER_DISPCTRL_DSP1EISLUR            BIT(14)
+# define SCALER_DISPCTRL_DSP3_MUX_MASK         VC4_MASK(19, 18)
+# define SCALER_DISPCTRL_DSP3_MUX_SHIFT                18
+
 /* Enables Display 0 short line and underrun contribution to
  * SCALER_DISPSTAT_IRQDISP0.  Note that short frame contributions are
  * always enabled.