clocksource: sh_cmt: Replace hardcoded register values with macros

Define symbolic macros for all used registers bits.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 879b8c2ae5564ff0405b432d5633dce4860e664f..ce00baaf8bd2126a199e49a65a80e7e71ed741db 100644 (file)
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -114,6 +114,34 @@ struct sh_cmt_device {
        unsigned int num_channels;
 };
 
+#define SH_CMT16_CMCSR_CMF             (1 << 7)
+#define SH_CMT16_CMCSR_CMIE            (1 << 6)
+#define SH_CMT16_CMCSR_CKS8            (0 << 0)
+#define SH_CMT16_CMCSR_CKS32           (1 << 0)
+#define SH_CMT16_CMCSR_CKS128          (2 << 0)
+#define SH_CMT16_CMCSR_CKS512          (3 << 0)
+#define SH_CMT16_CMCSR_CKS_MASK                (3 << 0)
+
+#define SH_CMT32_CMCSR_CMF             (1 << 15)
+#define SH_CMT32_CMCSR_OVF             (1 << 14)
+#define SH_CMT32_CMCSR_WRFLG           (1 << 13)
+#define SH_CMT32_CMCSR_STTF            (1 << 12)
+#define SH_CMT32_CMCSR_STPF            (1 << 11)
+#define SH_CMT32_CMCSR_SSIE            (1 << 10)
+#define SH_CMT32_CMCSR_CMS             (1 << 9)
+#define SH_CMT32_CMCSR_CMM             (1 << 8)
+#define SH_CMT32_CMCSR_CMTOUT_IE       (1 << 7)
+#define SH_CMT32_CMCSR_CMR_NONE                (0 << 4)
+#define SH_CMT32_CMCSR_CMR_DMA         (1 << 4)
+#define SH_CMT32_CMCSR_CMR_IRQ         (2 << 4)
+#define SH_CMT32_CMCSR_CMR_MASK                (3 << 4)
+#define SH_CMT32_CMCSR_DBGIVD          (1 << 3)
+#define SH_CMT32_CMCSR_CKS_RCLK8       (4 << 0)
+#define SH_CMT32_CMCSR_CKS_RCLK32      (5 << 0)
+#define SH_CMT32_CMCSR_CKS_RCLK128     (6 << 0)
+#define SH_CMT32_CMCSR_CKS_RCLK1       (7 << 0)
+#define SH_CMT32_CMCSR_CKS_MASK                (7 << 0)
+
 static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
 {
        return ioread16(base + (offs << 1));
@@ -140,8 +168,8 @@ static const struct sh_cmt_info sh_cmt_info[] = {
        [SH_CMT_16BIT] = {
                .model = SH_CMT_16BIT,
                .width = 16,
-               .overflow_bit = 0x80,
-               .clear_bits = ~0x80,
+               .overflow_bit = SH_CMT16_CMCSR_CMF,
+               .clear_bits = ~SH_CMT16_CMCSR_CMF,
                .read_control = sh_cmt_read16,
                .write_control = sh_cmt_write16,
                .read_count = sh_cmt_read16,
@@ -150,8 +178,8 @@ static const struct sh_cmt_info sh_cmt_info[] = {
        [SH_CMT_32BIT] = {
                .model = SH_CMT_32BIT,
                .width = 32,
-               .overflow_bit = 0x8000,
-               .clear_bits = ~0xc000,
+               .overflow_bit = SH_CMT32_CMCSR_CMF,
+               .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
                .read_control = sh_cmt_read16,
                .write_control = sh_cmt_write16,
                .read_count = sh_cmt_read32,
@@ -160,8 +188,8 @@ static const struct sh_cmt_info sh_cmt_info[] = {
        [SH_CMT_32BIT_FAST] = {
                .model = SH_CMT_32BIT_FAST,
                .width = 32,
-               .overflow_bit = 0x8000,
-               .clear_bits = ~0xc000,
+               .overflow_bit = SH_CMT32_CMCSR_CMF,
+               .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
                .read_control = sh_cmt_read16,
                .write_control = sh_cmt_write16,
                .read_count = sh_cmt_read32,
@@ -170,8 +198,8 @@ static const struct sh_cmt_info sh_cmt_info[] = {
        [SH_CMT_48BIT] = {
                .model = SH_CMT_48BIT,
                .width = 32,
-               .overflow_bit = 0x8000,
-               .clear_bits = ~0xc000,
+               .overflow_bit = SH_CMT32_CMCSR_CMF,
+               .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
                .read_control = sh_cmt_read32,
                .write_control = sh_cmt_write32,
                .read_count = sh_cmt_read32,
@@ -180,8 +208,8 @@ static const struct sh_cmt_info sh_cmt_info[] = {
        [SH_CMT_48BIT_GEN2] = {
                .model = SH_CMT_48BIT_GEN2,
                .width = 32,
-               .overflow_bit = 0x8000,
-               .clear_bits = ~0xc000,
+               .overflow_bit = SH_CMT32_CMCSR_CMF,
+               .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
                .read_control = sh_cmt_read32,
                .write_control = sh_cmt_write32,
                .read_count = sh_cmt_read32,
@@ -295,10 +323,14 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate)
        /* configure channel, periodic mode and maximum timeout */
        if (ch->cmt->info->width == 16) {
                *rate = clk_get_rate(ch->cmt->clk) / 512;
-               sh_cmt_write_cmcsr(ch, 0x43);
+               sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
+                                  SH_CMT16_CMCSR_CKS512);
        } else {
                *rate = clk_get_rate(ch->cmt->clk) / 8;
-               sh_cmt_write_cmcsr(ch, 0x01a4);
+               sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
+                                  SH_CMT32_CMCSR_CMTOUT_IE |
+                                  SH_CMT32_CMCSR_CMR_IRQ |
+                                  SH_CMT32_CMCSR_CKS_RCLK8);
        }
 
        sh_cmt_write_cmcor(ch, 0xffffffff);