mmc: sdhci-esdhc-imx: tuning bits should not be cleared during reset

We should not clear tuning bits during reset or the SD3.0/eMMC4.5 card
working on UHS mode may not work after reset since the former tuning
settings was lost.

Signed-off-by: Dong Aisheng <b29396@freescale.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <cjb@laptop.org>

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index d4ba277b572de6d41b76ce94e94fe7380ce6e8f7..d85a6a6f9e29849e4556de99114b8a66b06524a4 100644 (file)
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -45,6 +45,8 @@
 #define  ESDHC_MIX_CTRL_FBCLK_SEL      (1 << 25)
 /* Bits 3 and 6 are not SDHCI standard definitions */
 #define  ESDHC_MIX_CTRL_SDHCI_MASK     0xb7
+/* Tuning bits */
+#define  ESDHC_MIX_CTRL_TUNING_MASK    0x03c00000
 
 /* dll control register */
 #define ESDHC_DLL_CTRL                 0x60
@@ -562,7 +564,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
                 * Do it manually here.
                 */
                if (esdhc_is_usdhc(imx_data)) {
-                       writel(0, host->ioaddr + ESDHC_MIX_CTRL);
+                       /* the tuning bits should be kept during reset */
+                       new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
+                       writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
+                                       host->ioaddr + ESDHC_MIX_CTRL);
                        imx_data->is_ddr = 0;
                }
        }