machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_MX1) := mx1
-machine-$(CONFIG_ARCH_MX2) := mx2
+machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := mx25
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX5) := mx5
--- /dev/null
+if ARCH_MX2
+
+choice
+ prompt "CPUs:"
+ default MACH_MX21
+
+config MACH_MX21
+ bool "i.MX21 support"
+ select ARCH_MXC_AUDMUX_V1
+ help
+ This enables support for Freescale's MX2 based i.MX21 processor.
+
+config MACH_MX27
+ bool "i.MX27 support"
+ select ARCH_MXC_AUDMUX_V1
+ help
+ This enables support for Freescale's MX2 based i.MX27 processor.
+
+endchoice
+
+comment "MX2 platforms:"
+
+config MACH_MX21ADS
+ bool "MX21ADS platform"
+ depends on MACH_MX21
+ help
+ Include support for MX21ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX27ADS
+ bool "MX27ADS platform"
+ depends on MACH_MX27
+ help
+ Include support for MX27ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_PCM038
+ bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+ depends on MACH_MX27
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for phyCORE-i.MX27 (aka pcm038) platform. This
+ includes specific configurations for the module and its peripherals.
+
+choice
+ prompt "Baseboard"
+ depends on MACH_PCM038
+ default MACH_PCM970_BASEBOARD
+
+config MACH_PCM970_BASEBOARD
+ prompt "PHYTEC PCM970 development board"
+ bool
+ help
+ This adds board specific devices that can be found on Phytec's
+ PCM970 evaluation board.
+
+endchoice
+
+config MACH_CPUIMX27
+ bool "Eukrea CPUIMX27 module"
+ depends on MACH_MX27
+ help
+ Include support for Eukrea CPUIMX27 platform. This includes
+ specific configurations for the module and its peripherals.
+
+config MACH_EUKREA_CPUIMX27_USESDHC2
+ bool "CPUIMX27 integrates SDHC2 module"
+ depends on MACH_CPUIMX27
+ help
+ This adds support for the internal SDHC2 used on CPUIMX27 used
+ for wifi or eMMC.
+
+choice
+ prompt "Baseboard"
+ depends on MACH_CPUIMX27
+ default MACH_EUKREA_MBIMX27_BASEBOARD
+
+config MACH_EUKREA_MBIMX27_BASEBOARD
+ prompt "Eukrea MBIMX27 development board"
+ bool
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMX27 evaluation board.
+
+endchoice
+
+config MACH_MX27_3DS
+ bool "MX27PDK platform"
+ depends on MACH_MX27
+ help
+ Include support for MX27PDK platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_IMX27LITE
+ bool "LogicPD MX27 LITEKIT platform"
+ depends on MACH_MX27
+ help
+ Include support for MX27 LITEKIT platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_PCA100
+ bool "Phytec phyCARD-s (pca100)"
+ depends on MACH_MX27
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for phyCARD-s (aka pca100) platform. This
+ includes specific configurations for the module and its peripherals.
+
+config MACH_MXT_TD60
+ bool "Maxtrack i-MXT TD60"
+ depends on MACH_MX27
+ help
+ Include support for i-MXT (aka td60) platform. This
+ includes specific configurations for the module and its peripherals.
+
+endif
--- /dev/null
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y := devices.o serial.o
+
+obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+
+obj-$(CONFIG_MACH_MX27) += cpu-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+
+obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
+obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
+obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
+obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
+obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
+obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
+obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
+obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
--- /dev/null
+zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
+params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
+initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
+
+zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
+params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
+initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
--- /dev/null
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+
+#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
+#define CCM_PCDR0 IO_ADDR_CCM(0x18)
+#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0 IO_ADDR_CCM(0x20)
+#define CCM_PCCR1 IO_ADDR_CCM(0x24)
+#define CCM_CCSR IO_ADDR_CCM(0x28)
+#define CCM_PMCTL IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_PRESC_OFFSET 29
+#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
+
+#define CCM_CSCR_USB_OFFSET 26
+#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
+#define CCM_CSCR_SD_OFFSET 24
+#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
+#define CCM_CSCR_SPLLRES (1 << 22)
+#define CCM_CSCR_MPLLRES (1 << 21)
+#define CCM_CSCR_SSI2_OFFSET 20
+#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
+#define CCM_CSCR_SSI1_OFFSET 19
+#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
+#define CCM_CSCR_FIR_OFFSET 18
+#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
+#define CCM_CSCR_SP (1 << 17)
+#define CCM_CSCR_MCU (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET 10
+#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
+#define CCM_CSCR_IPDIV_OFFSET 9
+#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
+
+#define CCM_CSCR_OSC26MDIV (1 << 4)
+#define CCM_CSCR_OSC26M (1 << 3)
+#define CCM_CSCR_FPM (1 << 2)
+#define CCM_CSCR_SPEN (1 << 1)
+#define CCM_CSCR_MPEN 1
+
+#define CCM_MPCTL0_CPLM (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET 26
+#define CCM_MPCTL0_PD_MASK (0xf << 26)
+#define CCM_MPCTL0_MFD_OFFSET 16
+#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
+#define CCM_MPCTL0_MFI_OFFSET 10
+#define CCM_MPCTL0_MFI_MASK (0xf << 10)
+#define CCM_MPCTL0_MFN_OFFSET 0
+#define CCM_MPCTL0_MFN_MASK 0x3ff
+
+#define CCM_MPCTL1_LF (1 << 15)
+#define CCM_MPCTL1_BRMO (1 << 6)
+
+#define CCM_SPCTL0_CPLM (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET 26
+#define CCM_SPCTL0_PD_MASK (0xf << 26)
+#define CCM_SPCTL0_MFD_OFFSET 16
+#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
+#define CCM_SPCTL0_MFI_OFFSET 10
+#define CCM_SPCTL0_MFI_MASK (0xf << 10)
+#define CCM_SPCTL0_MFN_OFFSET 0
+#define CCM_SPCTL0_MFN_MASK 0x3ff
+
+#define CCM_SPCTL1_LF (1 << 15)
+#define CCM_SPCTL1_BRMO (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET 16
+#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET 8
+#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
+#define CCM_OSC26MCTL_ANATEST_OFFSET 0
+#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
+#define CCM_PCDR0_NFCDIV_OFFSET 12
+#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
+#define CCM_PCDR0_48MDIV_OFFSET 5
+#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
+#define CCM_PCDR0_FIRIDIV_OFFSET 0
+#define CCM_PCDR0_FIRIDIV_MASK 0x1f
+#define CCM_PCDR1_PERDIV4_OFFSET 24
+#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET 16
+#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET 8
+#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET 0
+#define CCM_PCDR1_PERDIV1_MASK 0x3f
+
+#define CCM_PCCR_HCLK_CSI_OFFSET 31
+#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_DMA_OFFSET 30
+#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_BROM_OFFSET 28
+#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_EMMA_OFFSET 27
+#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_LCDC_OFFSET 26
+#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
+#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
+#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_BMI_OFFSET 23
+#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
+#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
+#define CCM_PCCR_PERCLK4_OFFSET 22
+#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
+#define CCM_PCCR_SLCDC_OFFSET 21
+#define CCM_PCCR_SLCDC_REG CCM_PCCR0
+#define CCM_PCCR_FIRI_BAUD_OFFSET 20
+#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
+#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
+#define CCM_PCCR_NFC_OFFSET 19
+#define CCM_PCCR_NFC_REG CCM_PCCR0
+#define CCM_PCCR_LCDC_OFFSET 18
+#define CCM_PCCR_LCDC_REG CCM_PCCR0
+#define CCM_PCCR_SSI1_BAUD_OFFSET 17
+#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
+#define CCM_PCCR_SSI2_BAUD_OFFSET 16
+#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
+#define CCM_PCCR_EMMA_OFFSET 15
+#define CCM_PCCR_EMMA_REG CCM_PCCR0
+#define CCM_PCCR_USBOTG_OFFSET 14
+#define CCM_PCCR_USBOTG_REG CCM_PCCR0
+#define CCM_PCCR_DMA_OFFSET 13
+#define CCM_PCCR_DMA_REG CCM_PCCR0
+#define CCM_PCCR_I2C1_OFFSET 12
+#define CCM_PCCR_I2C1_REG CCM_PCCR0
+#define CCM_PCCR_GPIO_OFFSET 11
+#define CCM_PCCR_GPIO_REG CCM_PCCR0
+#define CCM_PCCR_SDHC2_OFFSET 10
+#define CCM_PCCR_SDHC2_REG CCM_PCCR0
+#define CCM_PCCR_SDHC1_OFFSET 9
+#define CCM_PCCR_SDHC1_REG CCM_PCCR0
+#define CCM_PCCR_FIRI_OFFSET 8
+#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
+#define CCM_PCCR_FIRI_REG CCM_PCCR0
+#define CCM_PCCR_SSI2_IPG_OFFSET 7
+#define CCM_PCCR_SSI2_REG CCM_PCCR0
+#define CCM_PCCR_SSI1_IPG_OFFSET 6
+#define CCM_PCCR_SSI1_REG CCM_PCCR0
+#define CCM_PCCR_CSPI2_OFFSET 5
+#define CCM_PCCR_CSPI2_REG CCM_PCCR0
+#define CCM_PCCR_CSPI1_OFFSET 4
+#define CCM_PCCR_CSPI1_REG CCM_PCCR0
+#define CCM_PCCR_UART4_OFFSET 3
+#define CCM_PCCR_UART4_REG CCM_PCCR0
+#define CCM_PCCR_UART3_OFFSET 2
+#define CCM_PCCR_UART3_REG CCM_PCCR0
+#define CCM_PCCR_UART2_OFFSET 1
+#define CCM_PCCR_UART2_REG CCM_PCCR0
+#define CCM_PCCR_UART1_OFFSET 0
+#define CCM_PCCR_UART1_REG CCM_PCCR0
+
+#define CCM_PCCR_OWIRE_OFFSET 31
+#define CCM_PCCR_OWIRE_REG CCM_PCCR1
+#define CCM_PCCR_KPP_OFFSET 30
+#define CCM_PCCR_KPP_REG CCM_PCCR1
+#define CCM_PCCR_RTC_OFFSET 29
+#define CCM_PCCR_RTC_REG CCM_PCCR1
+#define CCM_PCCR_PWM_OFFSET 28
+#define CCM_PCCR_PWM_REG CCM_PCCR1
+#define CCM_PCCR_GPT3_OFFSET 27
+#define CCM_PCCR_GPT3_REG CCM_PCCR1
+#define CCM_PCCR_GPT2_OFFSET 26
+#define CCM_PCCR_GPT2_REG CCM_PCCR1
+#define CCM_PCCR_GPT1_OFFSET 25
+#define CCM_PCCR_GPT1_REG CCM_PCCR1
+#define CCM_PCCR_WDT_OFFSET 24
+#define CCM_PCCR_WDT_REG CCM_PCCR1
+#define CCM_PCCR_CSPI3_OFFSET 23
+#define CCM_PCCR_CSPI3_REG CCM_PCCR1
+
+#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
+#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
+#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
+#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
+#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
+#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
+#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
+#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
+#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
+#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
+#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
+#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
+#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
+#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
+#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
+#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
+#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
+#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
+#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
+#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
+#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
+#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
+#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
+#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
+#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
+#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
+#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
+#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
+#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
+#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
+#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
+#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
+#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
+#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
+#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
+#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
+#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
+
+#define CCM_CCSR_32KSR (1 << 15)
+
+#define CCM_CCSR_CLKMODE1 (1 << 9)
+#define CCM_CCSR_CLKMODE0 (1 << 8)
+
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK 0x1f
+
+#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
+#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
+
+static int _clk_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+ return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long _clk_generic_round_rate(struct clk *clk,
+ unsigned long rate,
+ u32 max_divisor)
+{
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ if (div > max_divisor)
+ div = max_divisor;
+
+ return parent_rate / div;
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg |= CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+
+ while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
+ ;
+ return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg &= ~CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+}
+
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ return _clk_generic_round_rate(clk, rate, 64);
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->id < 0 || clk->id > 3)
+ return -EINVAL;
+
+ div = parent_rate / rate;
+ if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+ div--;
+
+ reg =
+ __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+ (clk->id << 3));
+ reg |= div << (clk->id << 3);
+ __raw_writel(reg, CCM_PCDR1);
+
+ return 0;
+}
+
+static unsigned long _clk_usb_recalc(struct clk *clk)
+{
+ unsigned long usb_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+ return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long _clk_usb_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ return _clk_generic_round_rate(clk, rate, 8);
+}
+
+static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+ div--;
+
+ reg = CSCR() & ~CCM_CSCR_USB_MASK;
+ reg |= div << CCM_CSCR_USB_OFFSET;
+ __raw_writel(reg, CCM_CSCR);
+
+ return 0;
+}
+
+static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
+{
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
+
+ return 2UL * parent_rate / pdf;
+}
+
+static unsigned long _clk_ssi1_recalc(struct clk *clk)
+{
+ return _clk_ssix_recalc(clk,
+ (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
+ >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
+}
+
+static unsigned long _clk_ssi2_recalc(struct clk *clk)
+{
+ return _clk_ssix_recalc(clk,
+ (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+ CCM_PCDR0_SSI2BAUDDIV_OFFSET);
+}
+
+static unsigned long _clk_nfc_recalc(struct clk *clk)
+{
+ unsigned long nfc_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
+ >> CCM_PCDR0_NFCDIV_OFFSET;
+
+ return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+ return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+ return clk->parent->set_rate(clk->parent, rate);
+}
+
+static unsigned long external_high_reference; /* in Hz */
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+ return external_high_reference;
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz.
+ */
+static struct clk ckih_clk = {
+ .get_rate = get_high_reference_clock_rate,
+};
+
+static unsigned long external_low_reference; /* in Hz */
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+ return external_low_reference;
+}
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+static struct clk ckil_clk = {
+ .get_rate = get_low_reference_clock_rate,
+};
+
+
+static unsigned long _clk_fpm_recalc(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) * 512;
+}
+
+/* Output of frequency pre multiplier */
+static struct clk fpm_clk = {
+ .parent = &ckil_clk,
+ .get_rate = _clk_fpm_recalc,
+};
+
+static unsigned long get_mpll_clk(struct clk *clk)
+{
+ uint32_t reg;
+ unsigned long ref_clk;
+ unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+ unsigned long long temp;
+
+ ref_clk = clk_get_rate(clk->parent);
+
+ reg = __raw_readl(CCM_MPCTL0);
+ pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
+ mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+ mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+ mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+
+ mfi = (mfi <= 5) ? 5 : mfi;
+ temp = 2LL * ref_clk * mfn;
+ do_div(temp, mfd + 1);
+ temp = 2LL * ref_clk * mfi + temp;
+ do_div(temp, pdf + 1);
+
+ return (unsigned long)temp;
+}
+
+static struct clk mpll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = get_mpll_clk,
+};
+
+static unsigned long _clk_fclk_get_rate(struct clk *clk)
+{
+ unsigned long parent_rate;
+ u32 div;
+
+ div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+ parent_rate = clk_get_rate(clk->parent);
+
+ return parent_rate / (div+1);
+}
+
+static struct clk fclk_clk = {
+ .parent = &mpll_clk,
+ .get_rate = _clk_fclk_get_rate
+};
+
+static unsigned long get_spll_clk(struct clk *clk)
+{
+ uint32_t reg;
+ unsigned long ref_clk;
+ unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+ unsigned long long temp;
+
+ ref_clk = clk_get_rate(clk->parent);
+
+ reg = __raw_readl(CCM_SPCTL0);
+ pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+ mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+ mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+ mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+
+ mfi = (mfi <= 5) ? 5 : mfi;
+ temp = 2LL * ref_clk * mfn;
+ do_div(temp, mfd + 1);
+ temp = 2LL * ref_clk * mfi + temp;
+ do_div(temp, pdf + 1);
+
+ return (unsigned long)temp;
+}
+
+static struct clk spll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = get_spll_clk,
+ .enable = _clk_spll_enable,
+ .disable = _clk_spll_disable,
+};
+
+static unsigned long get_hclk_clk(struct clk *clk)
+{
+ unsigned long rate;
+ unsigned long bclk_pdf;
+
+ bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
+ >> CCM_CSCR_BCLK_OFFSET;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (bclk_pdf + 1);
+}
+
+static struct clk hclk_clk = {
+ .parent = &fclk_clk,
+ .get_rate = get_hclk_clk,
+};
+
+static unsigned long get_ipg_clk(struct clk *clk)
+{
+ unsigned long rate;
+ unsigned long ipg_pdf;
+
+ ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (ipg_pdf + 1);
+}
+
+static struct clk ipg_clk = {
+ .parent = &hclk_clk,
+ .get_rate = get_ipg_clk,
+};
+
+static unsigned long _clk_perclkx_recalc(struct clk *clk)
+{
+ unsigned long perclk_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->id < 0 || clk->id > 3)
+ return 0;
+
+ perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+ return parent_rate / (perclk_pdf + 1);
+}
+
+static struct clk per_clk[] = {
+ {
+ .id = 0,
+ .parent = &mpll_clk,
+ .get_rate = _clk_perclkx_recalc,
+ }, {
+ .id = 1,
+ .parent = &mpll_clk,
+ .get_rate = _clk_perclkx_recalc,
+ }, {
+ .id = 2,
+ .parent = &mpll_clk,
+ .round_rate = _clk_perclkx_round_rate,
+ .set_rate = _clk_perclkx_set_rate,
+ .get_rate = _clk_perclkx_recalc,
+ /* Enable/Disable done via lcd_clkc[1] */
+ }, {
+ .id = 3,
+ .parent = &mpll_clk,
+ .round_rate = _clk_perclkx_round_rate,
+ .set_rate = _clk_perclkx_set_rate,
+ .get_rate = _clk_perclkx_recalc,
+ /* Enable/Disable done via csi_clk[1] */
+ },
+};
+
+static struct clk uart_ipg_clk[];
+
+static struct clk uart_clk[] = {
+ {
+ .id = 0,
+ .parent = &per_clk[0],
+ .secondary = &uart_ipg_clk[0],
+ }, {
+ .id = 1,
+ .parent = &per_clk[0],
+ .secondary = &uart_ipg_clk[1],
+ }, {
+ .id = 2,
+ .parent = &per_clk[0],
+ .secondary = &uart_ipg_clk[2],
+ }, {
+ .id = 3,
+ .parent = &per_clk[0],
+ .secondary = &uart_ipg_clk[3],
+ },
+};
+
+static struct clk uart_ipg_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_UART1_REG,
+ .enable_shift = CCM_PCCR_UART1_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_UART2_REG,
+ .enable_shift = CCM_PCCR_UART2_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_UART3_REG,
+ .enable_shift = CCM_PCCR_UART3_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 3,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_UART4_REG,
+ .enable_shift = CCM_PCCR_UART4_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk gpt_ipg_clk[];
+
+static struct clk gpt_clk[] = {
+ {
+ .id = 0,
+ .parent = &per_clk[0],
+ .secondary = &gpt_ipg_clk[0],
+ }, {
+ .id = 1,
+ .parent = &per_clk[0],
+ .secondary = &gpt_ipg_clk[1],
+ }, {
+ .id = 2,
+ .parent = &per_clk[0],
+ .secondary = &gpt_ipg_clk[2],
+ },
+};
+
+static struct clk gpt_ipg_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_GPT1_REG,
+ .enable_shift = CCM_PCCR_GPT1_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_GPT2_REG,
+ .enable_shift = CCM_PCCR_GPT2_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 2,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_GPT3_REG,
+ .enable_shift = CCM_PCCR_GPT3_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk pwm_clk[] = {
+ {
+ .parent = &per_clk[0],
+ .secondary = &pwm_clk[1],
+ }, {
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_PWM_REG,
+ .enable_shift = CCM_PCCR_PWM_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk sdhc_ipg_clk[];
+
+static struct clk sdhc_clk[] = {
+ {
+ .id = 0,
+ .parent = &per_clk[1],
+ .secondary = &sdhc_ipg_clk[0],
+ }, {
+ .id = 1,
+ .parent = &per_clk[1],
+ .secondary = &sdhc_ipg_clk[1],
+ },
+};
+
+static struct clk sdhc_ipg_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SDHC1_REG,
+ .enable_shift = CCM_PCCR_SDHC1_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SDHC2_REG,
+ .enable_shift = CCM_PCCR_SDHC2_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk cspi_ipg_clk[];
+
+static struct clk cspi_clk[] = {
+ {
+ .id = 0,
+ .parent = &per_clk[1],
+ .secondary = &cspi_ipg_clk[0],
+ }, {
+ .id = 1,
+ .parent = &per_clk[1],
+ .secondary = &cspi_ipg_clk[1],
+ }, {
+ .id = 2,
+ .parent = &per_clk[1],
+ .secondary = &cspi_ipg_clk[2],
+ },
+};
+
+static struct clk cspi_ipg_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_CSPI1_REG,
+ .enable_shift = CCM_PCCR_CSPI1_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_CSPI2_REG,
+ .enable_shift = CCM_PCCR_CSPI2_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 3,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_CSPI3_REG,
+ .enable_shift = CCM_PCCR_CSPI3_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk lcdc_clk[] = {
+ {
+ .parent = &per_clk[2],
+ .secondary = &lcdc_clk[1],
+ .round_rate = _clk_parent_round_rate,
+ .set_rate = _clk_parent_set_rate,
+ }, {
+ .parent = &ipg_clk,
+ .secondary = &lcdc_clk[2],
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_LCDC_REG,
+ .enable_shift = CCM_PCCR_LCDC_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
+ .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk csi_clk[] = {
+ {
+ .parent = &per_clk[3],
+ .secondary = &csi_clk[1],
+ .round_rate = _clk_parent_round_rate,
+ .set_rate = _clk_parent_set_rate,
+ }, {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_CSI_REG,
+ .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk usb_clk[] = {
+ {
+ .parent = &spll_clk,
+ .secondary = &usb_clk[1],
+ .get_rate = _clk_usb_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_USBOTG_REG,
+ .enable_shift = CCM_PCCR_USBOTG_OFFSET,
+ .disable = _clk_disable,
+ .round_rate = _clk_usb_round_rate,
+ .set_rate = _clk_usb_set_rate,
+ }, {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
+ .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
+ .disable = _clk_disable,
+ }
+};
+
+static struct clk ssi_ipg_clk[];
+
+static struct clk ssi_clk[] = {
+ {
+ .id = 0,
+ .parent = &mpll_clk,
+ .secondary = &ssi_ipg_clk[0],
+ .get_rate = _clk_ssi1_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
+ .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 1,
+ .parent = &mpll_clk,
+ .secondary = &ssi_ipg_clk[1],
+ .get_rate = _clk_ssi2_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
+ .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk ssi_ipg_clk[] = {
+ {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SSI1_REG,
+ .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
+ .disable = _clk_disable,
+ }, {
+ .id = 1,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SSI2_REG,
+ .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+
+static struct clk nfc_clk = {
+ .parent = &fclk_clk,
+ .get_rate = _clk_nfc_recalc,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_NFC_REG,
+ .enable_shift = CCM_PCCR_NFC_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk dma_clk[] = {
+ {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_DMA_REG,
+ .enable_shift = CCM_PCCR_DMA_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &dma_clk[1],
+ }, {
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_DMA_REG,
+ .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
+ .disable = _clk_disable,
+ },
+};
+
+static struct clk brom_clk = {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_BROM_REG,
+ .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk emma_clk[] = {
+ {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_EMMA_REG,
+ .enable_shift = CCM_PCCR_EMMA_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &emma_clk[1],
+ }, {
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
+ .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
+ .disable = _clk_disable,
+ }
+};
+
+static struct clk slcdc_clk[] = {
+ {
+ .parent = &hclk_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_SLCDC_REG,
+ .enable_shift = CCM_PCCR_SLCDC_OFFSET,
+ .disable = _clk_disable,
+ .secondary = &slcdc_clk[1],
+ }, {
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
+ .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
+ .disable = _clk_disable,
+ }
+};
+
+static struct clk wdog_clk = {
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_WDT_REG,
+ .enable_shift = CCM_PCCR_WDT_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_GPIO_REG,
+ .enable_shift = CCM_PCCR_GPIO_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk i2c_clk = {
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_I2C1_REG,
+ .enable_shift = CCM_PCCR_I2C1_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_KPP_REG,
+ .enable_shift = CCM_PCCR_KPP_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_OWIRE_REG,
+ .enable_shift = CCM_PCCR_OWIRE_OFFSET,
+ .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+ .parent = &ipg_clk,
+ .enable = _clk_enable,
+ .enable_reg = CCM_PCCR_RTC_REG,
+ .enable_shift = CCM_PCCR_RTC_OFFSET,
+ .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+ return _clk_generic_round_rate(clk, rate, 8);
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+ div--;
+
+ reg = __raw_readl(CCM_PCDR0);
+
+ if (clk->parent == &usb_clk[0]) {
+ reg &= ~CCM_PCDR0_48MDIV_MASK;
+ reg |= div << CCM_PCDR0_48MDIV_OFFSET;
+ }
+ __raw_writel(reg, CCM_PCDR0);
+
+ return 0;
+}
+
+static unsigned long _clk_clko_recalc(struct clk *clk)
+{
+ u32 div = 0;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->parent == &usb_clk[0]) /* 48M */
+ div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
+ >> CCM_PCDR0_48MDIV_OFFSET;
+ div++;
+
+ return parent_rate / div;
+}
+
+static struct clk clko_clk;
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+ if (parent == &ckil_clk)
+ reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &fpm_clk)
+ reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &ckih_clk)
+ reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == mpll_clk.parent)
+ reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == spll_clk.parent)
+ reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &mpll_clk)
+ reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &spll_clk)
+ reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &fclk_clk)
+ reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &hclk_clk)
+ reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &ipg_clk)
+ reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &per_clk[0])
+ reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &per_clk[1])
+ reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &per_clk[2])
+ reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &per_clk[3])
+ reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &ssi_clk[0])
+ reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &ssi_clk[1])
+ reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &nfc_clk)
+ reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &usb_clk[0])
+ reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
+ else if (parent == &clko_clk)
+ reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+ else
+ return -EINVAL;
+
+ __raw_writel(reg, CCM_CCSR);
+
+ return 0;
+}
+
+static struct clk clko_clk = {
+ .get_rate = _clk_clko_recalc,
+ .set_rate = _clk_clko_set_rate,
+ .round_rate = _clk_clko_round_rate,
+ .set_parent = _clk_clko_set_parent,
+};
+
+
+#define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ },
+static struct clk_lookup lookups[] = {
+/* It's unlikely that any driver wants one of them directly:
+ _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
+ _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
+ _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
+ _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
+ _REGISTER_CLOCK(NULL, "spll", spll_clk)
+ _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
+ _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
+ _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
+*/
+ _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
+ _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
+ _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
+ _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
+ _REGISTER_CLOCK(NULL, "clko", clko_clk)
+ _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+ _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+ _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+ _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3])
+ _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
+ _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
+ _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
+ _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
+ _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
+ _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
+ _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
+ _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
+ _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
+ _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
+ _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
+ _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
+ _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
+ _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
+ _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+ _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
+ _REGISTER_CLOCK(NULL, "brom", brom_clk)
+ _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
+ _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
+ _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+ _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+ _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+ _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+ _REGISTER_CLOCK(NULL, "owire", owire_clk)
+ _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+};
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx21_clocks_init(unsigned long lref, unsigned long href)
+{
+ u32 cscr;
+
+ external_low_reference = lref;
+ external_high_reference = href;
+
+ /* detect clock reference for both system PLL */
+ cscr = CSCR();
+ if (cscr & CCM_CSCR_MCU)
+ mpll_clk.parent = &ckih_clk;
+ else
+ mpll_clk.parent = &fpm_clk;
+
+ if (cscr & CCM_CSCR_SP)
+ spll_clk.parent = &ckih_clk;
+ else
+ spll_clk.parent = &fpm_clk;
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ /* Turn off all clock gates */
+ __raw_writel(0, CCM_PCCR0);
+ __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
+
+ /* This turns of the serial PLL as well */
+ spll_clk.disable(&spll_clk);
+
+ /* This will propagate to all children and init all the clock rates. */
+ clk_enable(&per_clk[0]);
+ clk_enable(&gpio_clk);
+
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+ clk_enable(&uart_clk[0]);
+#endif
+
+ mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
+ MX21_INT_GPT1);
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+/* Register offsets */
+#define CCM_CSCR IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
+#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
+#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
+#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
+#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
+#define CCM_PCDR0 IO_ADDR_CCM(0x18)
+#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
+#define CCM_PCCR0 IO_ADDR_CCM(0x20)
+#define CCM_PCCR1 IO_ADDR_CCM(0x24)
+#define CCM_CCSR IO_ADDR_CCM(0x28)
+#define CCM_PMCTL IO_ADDR_CCM(0x2c)
+#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
+#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
+
+#define CCM_CSCR_UPDATE_DIS (1 << 31)
+#define CCM_CSCR_SSI2 (1 << 23)
+#define CCM_CSCR_SSI1 (1 << 22)
+#define CCM_CSCR_VPU (1 << 21)
+#define CCM_CSCR_MSHC (1 << 20)
+#define CCM_CSCR_SPLLRES (1 << 19)
+#define CCM_CSCR_MPLLRES (1 << 18)
+#define CCM_CSCR_SP (1 << 17)
+#define CCM_CSCR_MCU (1 << 16)
+#define CCM_CSCR_OSC26MDIV (1 << 4)
+#define CCM_CSCR_OSC26M (1 << 3)
+#define CCM_CSCR_FPM (1 << 2)
+#define CCM_CSCR_SPEN (1 << 1)
+#define CCM_CSCR_MPEN (1 << 0)
+
+/* i.MX27 TO 2+ */
+#define CCM_CSCR_ARM_SRC (1 << 15)
+
+#define CCM_SPCTL1_LF (1 << 15)
+#define CCM_SPCTL1_BRMO (1 << 6)
+
+static struct clk mpll_main1_clk, mpll_main2_clk;
+
+static int clk_pccr_enable(struct clk *clk)
+{
+ unsigned long reg;
+
+ if (!clk->enable_reg)
+ return 0;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void clk_pccr_disable(struct clk *clk)
+{
+ unsigned long reg;
+
+ if (!clk->enable_reg)
+ return;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static int clk_spll_enable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg |= CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+
+ while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
+
+ return 0;
+}
+
+static void clk_spll_disable(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg &= ~CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+}
+
+static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+{
+ int cscr = __raw_readl(CCM_CSCR);
+
+ if (clk->parent == parent)
+ return 0;
+
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ if (parent == &mpll_main1_clk) {
+ cscr |= CCM_CSCR_ARM_SRC;
+ } else {
+ if (parent == &mpll_main2_clk)
+ cscr &= ~CCM_CSCR_ARM_SRC;
+ else
+ return -EINVAL;
+ }
+ __raw_writel(cscr, CCM_CSCR);
+ clk->parent = parent;
+ return 0;
+ }
+ return -ENODEV;
+}
+
+static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
+{
+ int div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ if (div > 4)
+ div = 4;
+
+ return parent_rate / div;
+}
+
+static int set_rate_cpu(struct clk *clk, unsigned long rate)
+{
+ unsigned int div;
+ uint32_t reg;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if (div > 4 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+
+ div--;
+
+ reg = __raw_readl(CCM_CSCR);
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ reg &= ~(3 << 12);
+ reg |= div << 12;
+ reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
+ __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
+ } else {
+ printk(KERN_ERR "Can't set CPU frequency!\n");
+ }
+
+ return 0;
+}
+
+static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
+{
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ if (div > 64)
+ div = 64;
+
+ return parent_rate / div;
+}
+
+static int set_rate_per(struct clk *clk, unsigned long rate)
+{
+ u32 reg;
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->id < 0 || clk->id > 3)
+ return -EINVAL;
+
+ div = parent_rate / rate;
+ if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+ div--;
+
+ reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
+ reg |= div << (clk->id << 3);
+ __raw_writel(reg, CCM_PCDR1);
+
+ return 0;
+}
+
+static unsigned long get_rate_usb(struct clk *clk)
+{
+ unsigned long usb_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
+
+ return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
+{
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ pdf += 4; /* MX27 TO2+ */
+ else
+ pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
+
+ return 2UL * parent_rate / pdf;
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+ return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
+}
+
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+ return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+ unsigned long nfc_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
+ else
+ nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
+
+ return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long get_rate_vpu(struct clk *clk)
+{
+ unsigned long vpu_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
+ vpu_pdf += 4;
+ } else {
+ vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
+ vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+ }
+
+ return 2UL * parent_rate / vpu_pdf;
+}
+
+static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
+{
+ return clk->parent->round_rate(clk->parent, rate);
+}
+
+static unsigned long get_rate_parent(struct clk *clk)
+{
+ return clk_get_rate(clk->parent);
+}
+
+static int set_rate_parent(struct clk *clk, unsigned long rate)
+{
+ return clk->parent->set_rate(clk->parent, rate);
+}
+
+/* in Hz */
+static unsigned long external_high_reference = 26000000;
+
+static unsigned long get_rate_high_reference(struct clk *clk)
+{
+ return external_high_reference;
+}
+
+/* in Hz */
+static unsigned long external_low_reference = 32768;
+
+static unsigned long get_rate_low_reference(struct clk *clk)
+{
+ return external_low_reference;
+}
+
+static unsigned long get_rate_fpm(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) * 1024;
+}
+
+static unsigned long get_rate_mpll(struct clk *clk)
+{
+ return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
+ clk_get_rate(clk->parent));
+}
+
+static unsigned long get_rate_mpll_main(struct clk *clk)
+{
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ /* i.MX27 TO2:
+ * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
+ * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
+ */
+ if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+ return 2UL * parent_rate / 3UL;
+
+ return parent_rate;
+}
+
+static unsigned long get_rate_spll(struct clk *clk)
+{
+ uint32_t reg;
+ unsigned long rate;
+
+ rate = clk_get_rate(clk->parent);
+
+ reg = __raw_readl(CCM_SPCTL0);
+
+ /* On TO2 we have to write the value back. Otherwise we
+ * read 0 from this register the next time.
+ */
+ if (mx27_revision() >= CHIP_REV_2_0)
+ __raw_writel(reg, CCM_SPCTL0);
+
+ return mxc_decode_pll(reg, rate);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+ u32 div;
+ unsigned long rate;
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
+ else
+ div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (div + 1);
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+ unsigned long rate, bclk_pdf;
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
+ else
+ bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (bclk_pdf + 1);
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+ unsigned long rate, ipg_pdf;
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ return clk_get_rate(clk->parent);
+ else
+ ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (ipg_pdf + 1);
+}
+
+static unsigned long get_rate_per(struct clk *clk)
+{
+ unsigned long perclk_pdf, parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->id < 0 || clk->id > 3)
+ return 0;
+
+ perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
+
+ return parent_rate / (perclk_pdf + 1);
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+static struct clk ckih_clk = {
+ .get_rate = get_rate_high_reference,
+};
+
+static struct clk mpll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = get_rate_mpll,
+};
+
+/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+ * It provides the clock source whose rate is same as MPLL
+ */
+static struct clk mpll_main1_clk = {
+ .id = 0,
+ .parent = &mpll_clk,
+ .get_rate = get_rate_mpll_main,
+};
+
+/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+ * It provides the clock source whose rate is same MPLL * 2 / 3
+ */
+static struct clk mpll_main2_clk = {
+ .id = 1,
+ .parent = &mpll_clk,
+ .get_rate = get_rate_mpll_main,
+};
+
+static struct clk ahb_clk = {
+ .parent = &mpll_main2_clk,
+ .get_rate = get_rate_ahb,
+};
+
+static struct clk ipg_clk = {
+ .parent = &ahb_clk,
+ .get_rate = get_rate_ipg,
+};
+
+static struct clk cpu_clk = {
+ .parent = &mpll_main2_clk,
+ .set_parent = clk_cpu_set_parent,
+ .round_rate = round_rate_cpu,
+ .get_rate = get_rate_cpu,
+ .set_rate = set_rate_cpu,
+};
+
+static struct clk spll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = get_rate_spll,
+ .enable = clk_spll_enable,
+ .disable = clk_spll_disable,
+};
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+static struct clk ckil_clk = {
+ .get_rate = get_rate_low_reference,
+};
+
+/* Output of frequency pre multiplier */
+static struct clk fpm_clk = {
+ .parent = &ckil_clk,
+ .get_rate = get_rate_fpm,
+};
+
+#define PCCR0 CCM_PCCR0
+#define PCCR1 CCM_PCCR1
+
+#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .get_rate = gr, \
+ .enable = clk_pccr_enable, \
+ .disable = clk_pccr_disable, \
+ .secondary = s, \
+ .parent = p, \
+ }
+
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .get_rate = get_rate_##getsetround, \
+ .set_rate = set_rate_##getsetround, \
+ .round_rate = round_rate_##getsetround, \
+ .enable = clk_pccr_enable, \
+ .disable = clk_pccr_disable, \
+ .secondary = s, \
+ .parent = p, \
+ }
+
+/* Forward declaration to keep the following list in order */
+static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
+ dma_clk1, lcdc_clk2, vpu_clk1;
+
+/* All clocks we can gate through PCCRx in the order of PCCRx bits */
+DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk);
+DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk);
+DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk);
+DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
+DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
+DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
+DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
+DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk);
+
+DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk);
+DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk);
+DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
+DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
+DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
+DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk);
+DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
+DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
+
+/* Clocks we cannot directly gate, but drivers need their rates */
+DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk);
+DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk);
+DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk);
+DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk);
+DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk);
+DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk);
+DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk);
+DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk);
+DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk);
+DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk);
+DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk);
+DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk);
+DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk);
+DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk);
+DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk);
+DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk);
+DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk);
+DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk);
+DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ },
+
+static struct clk_lookup lookups[] = {
+ _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+ _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
+ _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
+ _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
+ _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
+ _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
+ _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
+ _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
+ _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
+ _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+ _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+ _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
+ _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+ _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+ _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+ _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+ _REGISTER_CLOCK(NULL, "csi", csi_clk)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+ _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+ _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+ _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
+ _REGISTER_CLOCK(NULL, "dma", dma_clk)
+ _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+ _REGISTER_CLOCK(NULL, "brom", brom_clk)
+ _REGISTER_CLOCK(NULL, "emma", emma_clk)
+ _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
+ _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ _REGISTER_CLOCK(NULL, "emi", emi_clk)
+ _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
+ _REGISTER_CLOCK(NULL, "ata", ata_clk)
+ _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
+ _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+ _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+ _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+ _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+ _REGISTER_CLOCK(NULL, "iim", iim_clk)
+ _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+ _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+ _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+ _REGISTER_CLOCK(NULL, "scc", scc_clk)
+};
+
+/* Adjust the clock path for TO2 and later */
+static void __init to2_adjust_clocks(void)
+{
+ unsigned long cscr = __raw_readl(CCM_CSCR);
+
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ if (cscr & CCM_CSCR_ARM_SRC)
+ cpu_clk.parent = &mpll_main1_clk;
+
+ if (!(cscr & CCM_CSCR_SSI2))
+ ssi1_clk.parent = &spll_clk;
+
+ if (!(cscr & CCM_CSCR_SSI1))
+ ssi1_clk.parent = &spll_clk;
+
+ if (!(cscr & CCM_CSCR_VPU))
+ vpu_clk.parent = &spll_clk;
+ } else {
+ cpu_clk.parent = &mpll_clk;
+ cpu_clk.set_parent = NULL;
+ cpu_clk.round_rate = NULL;
+ cpu_clk.set_rate = NULL;
+ ahb_clk.parent = &mpll_clk;
+
+ per1_clk.parent = &mpll_clk;
+ per2_clk.parent = &mpll_clk;
+ per3_clk.parent = &mpll_clk;
+ per4_clk.parent = &mpll_clk;
+
+ ssi1_clk.parent = &mpll_clk;
+ ssi2_clk.parent = &mpll_clk;
+
+ vpu_clk.parent = &mpll_clk;
+ }
+}
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mx27_clocks_init(unsigned long fref)
+{
+ u32 cscr = __raw_readl(CCM_CSCR);
+
+ external_high_reference = fref;
+
+ /* detect clock reference for both system PLLs */
+ if (cscr & CCM_CSCR_MCU)
+ mpll_clk.parent = &ckih_clk;
+ else
+ mpll_clk.parent = &fpm_clk;
+
+ if (cscr & CCM_CSCR_SP)
+ spll_clk.parent = &ckih_clk;
+ else
+ spll_clk.parent = &fpm_clk;
+
+ to2_adjust_clocks();
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ /* Turn off all clocks we do not need */
+ __raw_writel(0, CCM_PCCR0);
+ __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
+
+ spll_clk.disable(&spll_clk);
+
+ /* enable basic clocks */
+ clk_enable(&per1_clk);
+ clk_enable(&gpio_clk);
+ clk_enable(&emi_clk);
+ clk_enable(&iim_clk);
+
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+ clk_enable(&uart1_clk);
+#endif
+
+ mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+ MX27_INT_GPT1);
+
+ return 0;
+}
+
--- /dev/null
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+/*
+ * i.MX27 specific CPU detection code
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <mach/hardware.h>
+
+static int cpu_silicon_rev = -1;
+static int cpu_partnumber;
+
+#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
+
+static void query_silicon_parameter(void)
+{
+ u32 val;
+ /*
+ * now we have access to the IO registers. As we need
+ * the silicon revision very early we read it here to
+ * avoid any further hooks
+ */
+ val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
+ + SYS_CHIP_ID));
+
+ cpu_silicon_rev = (int)(val >> 28);
+ cpu_partnumber = (int)((val >> 12) & 0xFFFF);
+}
+
+/*
+ * Returns:
+ * the silicon revision of the cpu
+ * -EINVAL - not a mx27
+ */
+int mx27_revision(void)
+{
+ if (cpu_silicon_rev == -1)
+ query_silicon_parameter();
+
+ if (cpu_partnumber != 0x8821)
+ return -EINVAL;
+
+ return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx27_revision);
--- /dev/null
+/*
+ * Author: MontaVista Software, Inc.
+ * <source@mvista.com>
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+/*
+ * SPI master controller
+ *
+ * - i.MX1: 2 channel (slighly different register setting)
+ * - i.MX21: 2 channel
+ * - i.MX27: 3 channel
+ */
+#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
+ static struct resource mxc_spi_resources ## n[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ }, \
+ }; \
+ \
+ struct platform_device mxc_spi_device ## n = { \
+ .name = "spi_imx", \
+ .id = n, \
+ .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
+ .resource = mxc_spi_resources ## n, \
+ }
+
+DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
+DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
+
+#ifdef CONFIG_MACH_MX27
+DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
+#endif
+
+/*
+ * General Purpose Timer
+ * - i.MX21: 3 timers
+ * - i.MX27: 6 timers
+ */
+#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
+ static struct resource timer ## n ##_resources[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }; \
+ \
+ struct platform_device mxc_gpt ## n = { \
+ .name = "imx_gpt", \
+ .id = n, \
+ .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
+ .resource = timer ## n ## _resources, \
+ }
+
+/* We use gpt1 as system timer, so do not add a device for this one */
+DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
+DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
+
+#ifdef CONFIG_MACH_MX27
+DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
+DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
+DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
+#endif
+
+/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
+static struct resource mxc_wdt_resources[] = {
+ {
+ .start = MX2x_WDOG_BASE_ADDR,
+ .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device mxc_wdt = {
+ .name = "imx2-wdt",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+ .resource = mxc_wdt_resources,
+};
+
+static struct resource mxc_w1_master_resources[] = {
+ {
+ .start = MX2x_OWIRE_BASE_ADDR,
+ .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device mxc_w1_master_device = {
+ .name = "mxc_w1",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
+ .resource = mxc_w1_master_resources,
+};
+
+#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
+ static struct resource pfx ## _nand_resources[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ }, \
+ }; \
+ \
+ struct platform_device pfx ## _nand_device = { \
+ .name = "mxc_nand", \
+ .id = 0, \
+ .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
+ .resource = pfx ## _nand_resources, \
+ }
+
+#ifdef CONFIG_MACH_MX21
+DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
+#endif
+
+#ifdef CONFIG_MACH_MX27
+DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
+#endif
+
+/*
+ * lcdc:
+ * - i.MX1: the basic controller
+ * - i.MX21: to be checked
+ * - i.MX27: like i.MX1, with slightly variations
+ */
+static struct resource mxc_fb[] = {
+ {
+ .start = MX2x_LCDC_BASE_ADDR,
+ .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_LCDC,
+ .end = MX2x_INT_LCDC,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+/* mxc lcd driver */
+struct platform_device mxc_fb_device = {
+ .name = "imx-fb",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_fb),
+ .resource = mxc_fb,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource mxc_fec_resources[] = {
+ {
+ .start = MX27_FEC_BASE_ADDR,
+ .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_FEC,
+ .end = MX27_INT_FEC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_fec_device = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_fec_resources),
+ .resource = mxc_fec_resources,
+};
+#endif
+
+#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
+ static struct resource mxc_i2c_resources ## n[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }; \
+ \
+ struct platform_device mxc_i2c_device ## n = { \
+ .name = "imx-i2c", \
+ .id = n, \
+ .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
+ .resource = mxc_i2c_resources ## n, \
+ }
+
+DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
+
+#ifdef CONFIG_MACH_MX27
+DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
+#endif
+
+static struct resource mxc_pwm_resources[] = {
+ {
+ .start = MX2x_PWM_BASE_ADDR,
+ .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_PWM,
+ .end = MX2x_INT_PWM,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device mxc_pwm_device = {
+ .name = "mxc_pwm",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_pwm_resources),
+ .resource = mxc_pwm_resources,
+};
+
+#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
+ static struct resource mxc_sdhc_resources ## n[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ }, { \
+ .start = dmareq, \
+ .end = dmareq, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ }; \
+ \
+ static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
+ \
+ struct platform_device mxc_sdhc_device ## n = { \
+ .name = "mxc-mmc", \
+ .id = n, \
+ .dev = { \
+ .dma_mask = &mxc_sdhc ## n ## _dmamask, \
+ .coherent_dma_mask = DMA_BIT_MASK(32), \
+ }, \
+ .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
+ .resource = mxc_sdhc_resources ## n, \
+ }
+
+DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
+DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
+
+#ifdef CONFIG_MACH_MX27
+static struct resource otg_resources[] = {
+ {
+ .start = MX27_USBOTG_BASE_ADDR,
+ .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_USB3,
+ .end = MX27_INT_USB3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 otg_dmamask = DMA_BIT_MASK(32);
+
+/* OTG gadget device */
+struct platform_device mxc_otg_udc_device = {
+ .name = "fsl-usb2-udc",
+ .id = -1,
+ .dev = {
+ .dma_mask = &otg_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+/* OTG host */
+struct platform_device mxc_otg_host = {
+ .name = "mxc-ehci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &otg_dmamask,
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+/* USB host 1 */
+
+static u64 usbh1_dmamask = DMA_BIT_MASK(32);
+
+static struct resource mxc_usbh1_resources[] = {
+ {
+ .start = MX27_USBOTG_BASE_ADDR + 0x200,
+ .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_USB1,
+ .end = MX27_INT_USB1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_usbh1 = {
+ .name = "mxc-ehci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &usbh1_dmamask,
+ },
+ .resource = mxc_usbh1_resources,
+ .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+
+/* USB host 2 */
+static u64 usbh2_dmamask = DMA_BIT_MASK(32);
+
+static struct resource mxc_usbh2_resources[] = {
+ {
+ .start = MX27_USBOTG_BASE_ADDR + 0x400,
+ .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_USB2,
+ .end = MX27_INT_USB2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_usbh2 = {
+ .name = "mxc-ehci",
+ .id = 2,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &usbh2_dmamask,
+ },
+ .resource = mxc_usbh2_resources,
+ .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+#endif
+
+#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
+ { \
+ .name = _name, \
+ .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
+ .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
+ .flags = IORESOURCE_DMA, \
+ }
+
+#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
+ static struct resource imx_ssi_resources ## n[] = { \
+ { \
+ .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
+ .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = MX2x_INT_SSI1, \
+ .end = MX2x_INT_SSI1, \
+ .flags = IORESOURCE_IRQ, \
+ }, \
+ DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
+ DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
+ DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
+ DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
+ }; \
+ \
+ struct platform_device imx_ssi_device ## n = { \
+ .name = "imx-ssi", \
+ .id = n, \
+ .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
+ .resource = imx_ssi_resources ## n, \
+ }
+
+DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
+DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
+
+/* GPIO port description */
+#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
+ { \
+ .chip.label = "gpio-" #n, \
+ .irq = _irq, \
+ .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
+ n * 0x100), \
+ .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
+ }
+
+#define DEFINE_MXC_GPIO_PORT(SOC, n) \
+ { \
+ .chip.label = "gpio-" #n, \
+ .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
+ n * 0x100), \
+ .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
+ }
+
+#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
+ static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
+ DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
+ DEFINE_MXC_GPIO_PORT(SOC, 1), \
+ DEFINE_MXC_GPIO_PORT(SOC, 2), \
+ DEFINE_MXC_GPIO_PORT(SOC, 3), \
+ DEFINE_MXC_GPIO_PORT(SOC, 4), \
+ DEFINE_MXC_GPIO_PORT(SOC, 5), \
+ }
+
+#ifdef CONFIG_MACH_MX21
+DEFINE_MXC_GPIO_PORTS(MX21, imx21);
+#endif
+
+#ifdef CONFIG_MACH_MX27
+DEFINE_MXC_GPIO_PORTS(MX27, imx27);
+#endif
+
+int __init mxc_register_gpios(void)
+{
+#ifdef CONFIG_MACH_MX21
+ if (cpu_is_mx21())
+ return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+ else
+#endif
+#ifdef CONFIG_MACH_MX27
+ if (cpu_is_mx27())
+ return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
+ else
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_MACH_MX21
+static struct resource mx21_usbhc_resources[] = {
+ {
+ .start = MX21_USBOTG_BASE_ADDR,
+ .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX21_INT_USBHOST,
+ .end = MX21_INT_USBHOST,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mx21_usbhc_device = {
+ .name = "imx21-hcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
+ .resource = mx21_usbhc_resources,
+};
+#endif
+
--- /dev/null
+extern struct platform_device mxc_gpt1;
+extern struct platform_device mxc_gpt2;
+#ifdef CONFIG_MACH_MX27
+extern struct platform_device mxc_gpt3;
+extern struct platform_device mxc_gpt4;
+extern struct platform_device mxc_gpt5;
+#endif
+extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_uart_device3;
+extern struct platform_device mxc_uart_device4;
+extern struct platform_device mxc_uart_device5;
+extern struct platform_device mxc_w1_master_device;
+#ifdef CONFIG_MACH_MX21
+extern struct platform_device imx21_nand_device;
+#endif
+#ifdef CONFIG_MACH_MX27
+extern struct platform_device imx27_nand_device;
+#endif
+extern struct platform_device mxc_fb_device;
+extern struct platform_device mxc_fec_device;
+extern struct platform_device mxc_pwm_device;
+extern struct platform_device mxc_i2c_device0;
+#ifdef CONFIG_MACH_MX27
+extern struct platform_device mxc_i2c_device1;
+#endif
+extern struct platform_device mxc_sdhc_device0;
+extern struct platform_device mxc_sdhc_device1;
+extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+#ifdef CONFIG_MACH_MX27
+extern struct platform_device mxc_spi_device2;
+#endif
+extern struct platform_device mx21_usbhc_device;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
--- /dev/null
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static int eukrea_mbimx27_pins[] = {
+ /* UART2 */
+ PE3_PF_UART2_CTS,
+ PE4_PF_UART2_RTS,
+ PE6_PF_UART2_TXD,
+ PE7_PF_UART2_RXD,
+ /* UART3 */
+ PE8_PF_UART3_TXD,
+ PE9_PF_UART3_RXD,
+ PE10_PF_UART3_CTS,
+ PE11_PF_UART3_RTS,
+ /* UART4 */
+ PB26_AF_UART4_RTS,
+ PB28_AF_UART4_TXD,
+ PB29_AF_UART4_CTS,
+ PB31_AF_UART4_RXD,
+ /* SDHC1*/
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+ /* display */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA23_PF_LD17,
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ PA31_PF_OE_ACD,
+ /* SPI1 */
+ PD28_PF_CSPI1_SS0,
+ PD29_PF_CSPI1_SCLK,
+ PD30_PF_CSPI1_MISO,
+ PD31_PF_CSPI1_MOSI,
+};
+
+static struct gpio_led gpio_leds[] = {
+ {
+ .name = "led1",
+ .default_trigger = "heartbeat",
+ .active_low = 1,
+ .gpio = GPIO_PORTF | 16,
+ },
+ {
+ .name = "led2",
+ .default_trigger = "none",
+ .active_low = 1,
+ .gpio = GPIO_PORTF | 19,
+ },
+ {
+ .name = "backlight",
+ .default_trigger = "backlight",
+ .active_low = 0,
+ .gpio = GPIO_PORTE | 5,
+ },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+};
+
+static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
+ {
+ .mode = {
+ .name = "CMO-QGVA",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = 156000,
+ .hsync_len = 30,
+ .left_margin = 38,
+ .right_margin = 20,
+ .vsync_len = 3,
+ .upper_margin = 15,
+ .lower_margin = 4,
+ },
+ .pcr = 0xFAD08B80,
+ .bpp = 16,
+ },
+};
+
+static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
+ .mode = eukrea_mbimx27_modes,
+ .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
+
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00040060,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+ {
+ .flags = IMXUART_HAVE_RTSCTS,
+ },
+ {
+ .flags = IMXUART_HAVE_RTSCTS,
+ },
+};
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+
+#define ADS7846_PENDOWN (GPIO_PORTD | 25)
+
+static void ads7846_dev_init(void)
+{
+ if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
+ printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+ return;
+ }
+
+ gpio_direction_input(ADS7846_PENDOWN);
+}
+
+static int ads7846_get_pendown_state(void)
+{
+ return !gpio_get_value(ADS7846_PENDOWN);
+}
+
+static struct ads7846_platform_data ads7846_config __initdata = {
+ .get_pendown_state = ads7846_get_pendown_state,
+ .keep_vref_on = 1,
+};
+
+static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+ [0] = {
+ .modalias = "ads7846",
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 1500000,
+ .irq = IRQ_GPIOD(25),
+ .platform_data = &ads7846_config,
+ .mode = SPI_MODE_2,
+ },
+};
+
+static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
+
+static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+ .chipselect = eukrea_mbimx27_spi_cs,
+ .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
+};
+#endif
+
+static struct platform_device *platform_devices[] __initdata = {
+ &leds_gpio,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx27 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimx27_baseboard_init(void)
+{
+ mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
+ ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
+
+ mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
+ mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+
+ mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
+ mxc_register_device(&mxc_sdhc_device0, NULL);
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ /* SPI and ADS7846 Touchscreen controler init */
+ mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+ mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
+ mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+ spi_register_board_info(eukrea_mbimx27_spi_board_info,
+ ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
+ ads7846_dev_init();
+#endif
+
+ /* Leds configuration */
+ mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
+ mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
+ /* Backlight */
+ mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
--- /dev/null
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm038.c which is :
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/iomux-mx27.h>
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+
+#include "devices.h"
+
+static int eukrea_cpuimx27_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* UART4 */
+ PB26_AF_UART4_RTS,
+ PB28_AF_UART4_TXD,
+ PB29_AF_UART4_CTS,
+ PB31_AF_UART4_RXD,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* I2C1 */
+ PD17_PF_I2C_DATA,
+ PD18_PF_I2C_CLK,
+ /* SDHC2 */
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ /* Quad UART's IRQ */
+ GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
+ GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
+ GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
+ GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+#endif
+};
+
+static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
+ .width = 2,
+};
+
+static struct resource eukrea_cpuimx27_flash_resource = {
+ .start = 0xc0000000,
+ .end = 0xc3ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &eukrea_cpuimx27_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &eukrea_cpuimx27_flash_resource,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+ {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ },
+};
+
+static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &eukrea_cpuimx27_nor_mtd_device,
+ &mxc_fec_device,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+ .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ },
+};
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+ {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
+ .irq = IRQ_GPIOB(23),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
+ .irq = IRQ_GPIOB(22),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
+ .irq = IRQ_GPIOB(27),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
+ .irq = IRQ_GPIOB(30),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ }
+};
+
+static struct platform_device serial_device = {
+ .name = "serial8250",
+ .id = 0,
+ .dev = {
+ .platform_data = serial_platform_data,
+ },
+};
+#endif
+
+static void __init eukrea_cpuimx27_init(void)
+{
+ mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
+ ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
+
+ mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+
+ mxc_register_device(&imx27_nand_device,
+ &eukrea_cpuimx27_nand_board_info);
+
+ i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
+ ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
+
+ mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
+ /* SDHC2 can be used for Wifi */
+ mxc_register_device(&mxc_sdhc_device1, NULL);
+ /* in which case UART4 is also used for Bluetooth */
+ mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+#endif
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ platform_device_register(&serial_device);
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
+ eukrea_mbimx27_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx27_timer_init(void)
+{
+ mx27_clocks_init(26000000);
+}
+
+static struct sys_timer eukrea_cpuimx27_timer = {
+ .init = eukrea_cpuimx27_timer_init,
+};
+
+MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = eukrea_cpuimx27_init,
+ .timer = &eukrea_cpuimx27_timer,
+MACHINE_END
--- /dev/null
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx27.h>
+
+#include "devices.h"
+
+static unsigned int mx27lite_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &mxc_fec_device,
+};
+
+static void __init mx27lite_init(void)
+{
+ mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
+ "imx27lite");
+ mxc_register_device(&mxc_uart_device0, &uart_pdata);
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx27lite_timer_init(void)
+{
+ mx27_clocks_init(26000000);
+}
+
+static struct sys_timer mx27lite_timer = {
+ .init = mx27lite_timer_init,
+};
+
+MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = mx27lite_init,
+ .timer = &mx27lite_timer,
+MACHINE_END
--- /dev/null
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/iomux-mx21.h>
+#include <mach/mxc_nand.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+/*
+ * Memory-mapped I/O on MX21ADS base board
+ */
+#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
+#define MX21ADS_MMIO_SIZE SZ_16M
+
+#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
+ (MX21ADS_MMIO_BASE_ADDR + (offset))
+
+#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
+#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
+#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
+
+/* MX21ADS_IO_REG bit definitions */
+#define MX21ADS_IO_SD_WP 0x0001 /* read */
+#define MX21ADS_IO_TP6 0x0001 /* write */
+#define MX21ADS_IO_SW_SEL 0x0002 /* read */
+#define MX21ADS_IO_TP7 0x0002 /* write */
+#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_BASE 0x0008
+#define MX21ADS_IO_CSI_CTL2 0x0010
+#define MX21ADS_IO_CSI_CTL1 0x0020
+#define MX21ADS_IO_CSI_CTL0 0x0040
+#define MX21ADS_IO_UART1_EN 0x0080
+#define MX21ADS_IO_UART4_EN 0x0100
+#define MX21ADS_IO_LCDON 0x0200
+#define MX21ADS_IO_IRDA_EN 0x0400
+#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_MD0_B 0x1000
+#define MX21ADS_IO_IRDA_MD1 0x2000
+#define MX21ADS_IO_LED4_ON 0x4000
+#define MX21ADS_IO_LED3_ON 0x8000
+
+static unsigned int mx21ads_pins[] = {
+
+ /* CS8900A */
+ (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
+
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+
+ /* UART3 (IrDA) - only TXD and RXD */
+ PE8_PF_UART3_TXD,
+ PE9_PF_UART3_RXD,
+
+ /* UART4 */
+ PB26_AF_UART4_RTS,
+ PB28_AF_UART4_TXD,
+ PB29_AF_UART4_CTS,
+ PB31_AF_UART4_RXD,
+
+ /* LCDC */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA24_PF_REV, /* Sharp panel dedicated signal */
+ PA25_PF_CLS, /* Sharp panel dedicated signal */
+ PA26_PF_PS, /* Sharp panel dedicated signal */
+ PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ PA31_PF_OE_ACD,
+
+ /* MMC/SDHC */
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+
+ /* NFC */
+ PF0_PF_NRFB,
+ PF1_PF_NFCE,
+ PF2_PF_NFWP,
+ PF3_PF_NFCLE,
+ PF4_PF_NFALE,
+ PF5_PF_NFRE,
+ PF6_PF_NFWE,
+ PF7_PF_NFIO0,
+ PF8_PF_NFIO1,
+ PF9_PF_NFIO2,
+ PF10_PF_NFIO3,
+ PF11_PF_NFIO4,
+ PF12_PF_NFIO5,
+ PF13_PF_NFIO6,
+ PF14_PF_NFIO7,
+};
+
+/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
+static struct physmap_flash_data mx21ads_flash_data = {
+ .width = 4,
+};
+
+static struct resource mx21ads_flash_resource = {
+ .start = MX21_CS0_BASE_ADDR,
+ .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device mx21ads_nor_mtd_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &mx21ads_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &mx21ads_flash_resource,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct imxuart_platform_data uart_norts_pdata = {
+};
+
+
+static int mx21ads_fb_init(struct platform_device *pdev)
+{
+ u16 tmp;
+
+ tmp = __raw_readw(MX21ADS_IO_REG);
+ tmp |= MX21ADS_IO_LCDON;
+ __raw_writew(tmp, MX21ADS_IO_REG);
+ return 0;
+}
+
+static void mx21ads_fb_exit(struct platform_device *pdev)
+{
+ u16 tmp;
+
+ tmp = __raw_readw(MX21ADS_IO_REG);
+ tmp &= ~MX21ADS_IO_LCDON;
+ __raw_writew(tmp, MX21ADS_IO_REG);
+}
+
+/*
+ * Connected is a portrait Sharp-QVGA display
+ * of type: LQ035Q7DB02
+ */
+static struct imx_fb_videomode mx21ads_modes[] = {
+ {
+ .mode = {
+ .name = "Sharp-LQ035Q7",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 188679, /* in ps (5.3MHz) */
+ .hsync_len = 2,
+ .left_margin = 6,
+ .right_margin = 16,
+ .vsync_len = 1,
+ .upper_margin = 8,
+ .lower_margin = 10,
+ },
+ .pcr = 0xfb108bc7,
+ .bpp = 16,
+ },
+};
+
+static struct imx_fb_platform_data mx21ads_fb_data = {
+ .mode = mx21ads_modes,
+ .num_modes = ARRAY_SIZE(mx21ads_modes),
+
+ .pwmr = 0x00a903ff,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00020008,
+
+ .init = mx21ads_fb_init,
+ .exit = mx21ads_fb_exit,
+};
+
+static int mx21ads_sdhc_get_ro(struct device *dev)
+{
+ return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
+}
+
+static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = request_irq(IRQ_GPIOD(25), detect_irq,
+ IRQF_TRIGGER_FALLING, "mmc-detect", data);
+ if (ret)
+ goto out;
+ return 0;
+out:
+ return ret;
+}
+
+static void mx21ads_sdhc_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOD(25), data);
+}
+
+static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
+ .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
+ .get_ro = mx21ads_sdhc_get_ro,
+ .init = mx21ads_sdhc_init,
+ .exit = mx21ads_sdhc_exit,
+};
+
+static struct mxc_nand_platform_data mx21ads_nand_board_info = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static struct map_desc mx21ads_io_desc[] __initdata = {
+ /*
+ * Memory-mapped I/O on MX21ADS Base board:
+ * - CS8900A Ethernet controller
+ * - ST16C2552CJ UART
+ * - CPU and Base board version
+ * - Base board I/O register
+ */
+ {
+ .virtual = MX21ADS_MMIO_BASE_ADDR,
+ .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
+ .length = MX21ADS_MMIO_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init mx21ads_map_io(void)
+{
+ mx21_map_io();
+ iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+ &mx21ads_nor_mtd_device,
+};
+
+static void __init mx21ads_board_init(void)
+{
+ mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
+ "mx21ads");
+
+ mxc_register_device(&mxc_uart_device0, &uart_pdata);
+ mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
+ mxc_register_device(&mxc_uart_device3, &uart_pdata);
+ mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
+ mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
+ mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx21ads_timer_init(void)
+{
+ mx21_clocks_init(32768, 26000000);
+}
+
+static struct sys_timer mx21ads_timer = {
+ .init = mx21ads_timer_init,
+};
+
+MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
+ /* maintainer: Freescale Semiconductor, Inc. */
+ .phys_io = MX21_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX21_PHYS_OFFSET + 0x100,
+ .map_io = mx21ads_map_io,
+ .init_irq = mx21_init_irq,
+ .init_machine = mx21ads_board_init,
+ .timer = &mx21ads_timer,
+MACHINE_END
--- /dev/null
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * This machine is known as:
+ * - i.MX27 3-Stack Development System
+ * - i.MX27 Platform Development Kit (i.MX27 PDK)
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx27.h>
+
+#include "devices.h"
+
+static unsigned int mx27pdk_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &mxc_fec_device,
+};
+
+static void __init mx27pdk_init(void)
+{
+ mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
+ "mx27pdk");
+ mxc_register_device(&mxc_uart_device0, &uart_pdata);
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx27pdk_timer_init(void)
+{
+ mx27_clocks_init(26000000);
+}
+
+static struct sys_timer mx27pdk_timer = {
+ .init = mx27pdk_timer_init,
+};
+
+MACHINE_START(MX27_3DS, "Freescale MX27PDK")
+ /* maintainer: Freescale Semiconductor, Inc. */
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = mx27pdk_init,
+ .timer = &mx27pdk_timer,
+MACHINE_END
--- /dev/null
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/gpio.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx27.h>
+#include <mach/mxc_nand.h>
+#include <mach/i2c.h>
+#include <mach/imxfb.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS 0xf4300000
+#define PBC_REG_ADDR(offset) (void __force __iomem *) \
+ (PBC_BASE_ADDRESS + (offset))
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH 0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET (1 << 3)
+
+static unsigned int mx27ads_pins[] = {
+ /* UART0 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* UART1 */
+ PE3_PF_UART2_CTS,
+ PE4_PF_UART2_RTS,
+ PE6_PF_UART2_TXD,
+ PE7_PF_UART2_RXD,
+ /* UART2 */
+ PE8_PF_UART3_TXD,
+ PE9_PF_UART3_RXD,
+ PE10_PF_UART3_CTS,
+ PE11_PF_UART3_RTS,
+ /* UART3 */
+ PB26_AF_UART4_RTS,
+ PB28_AF_UART4_TXD,
+ PB29_AF_UART4_CTS,
+ PB31_AF_UART4_RXD,
+ /* UART4 */
+ PB18_AF_UART5_TXD,
+ PB19_AF_UART5_RXD,
+ PB20_AF_UART5_CTS,
+ PB21_AF_UART5_RTS,
+ /* UART5 */
+ PB10_AF_UART6_TXD,
+ PB12_AF_UART6_CTS,
+ PB11_AF_UART6_RXD,
+ PB13_AF_UART6_RTS,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* I2C2 */
+ PC5_PF_I2C2_SDA,
+ PC6_PF_I2C2_SCL,
+ /* FB */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA23_PF_LD17,
+ PA24_PF_REV,
+ PA25_PF_CLS,
+ PA26_PF_PS,
+ PA27_PF_SPL_SPR,
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ PA31_PF_OE_ACD,
+ /* OWIRE */
+ PE16_AF_OWIRE,
+ /* SDHC1*/
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+ /* SDHC2*/
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+};
+
+static struct mxc_nand_platform_data mx27ads_nand_board_info = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+/* ADS's NOR flash */
+static struct physmap_flash_data mx27ads_flash_data = {
+ .width = 2,
+};
+
+static struct resource mx27ads_flash_resource = {
+ .start = 0xc0000000,
+ .end = 0xc0000000 + 0x02000000 - 1,
+ .flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mx27ads_nor_mtd_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &mx27ads_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &mx27ads_flash_resource,
+};
+
+static struct imxi2c_platform_data mx27ads_i2c_data = {
+ .bitrate = 100000,
+};
+
+static struct i2c_board_info mx27ads_i2c_devices[] = {
+};
+
+void lcd_power(int on)
+{
+ if (on)
+ __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
+ else
+ __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
+}
+
+static struct imx_fb_videomode mx27ads_modes[] = {
+ {
+ .mode = {
+ .name = "Sharp-LQ035Q7",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 188679, /* in ps (5.3MHz) */
+ .hsync_len = 1,
+ .left_margin = 9,
+ .right_margin = 16,
+ .vsync_len = 1,
+ .upper_margin = 7,
+ .lower_margin = 9,
+ },
+ .bpp = 16,
+ .pcr = 0xFB008BC0,
+ },
+};
+
+static struct imx_fb_platform_data mx27ads_fb_data = {
+ .mode = mx27ads_modes,
+ .num_modes = ARRAY_SIZE(mx27ads_modes),
+
+ /*
+ * - HSYNC active high
+ * - VSYNC active high
+ * - clk notenabled while idle
+ * - clock inverted
+ * - data not inverted
+ * - data enable low active
+ * - enable sharp mode
+ */
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00020010,
+
+ .lcd_power = lcd_power,
+};
+
+static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
+ "sdhc1-card-detect", data);
+}
+
+static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
+ "sdhc2-card-detect", data);
+}
+
+static void mx27ads_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOE(21), data);
+}
+
+static void mx27ads_sdhc2_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOB(7), data);
+}
+
+static struct imxmmc_platform_data sdhc1_pdata = {
+ .init = mx27ads_sdhc1_init,
+ .exit = mx27ads_sdhc1_exit,
+};
+
+static struct imxmmc_platform_data sdhc2_pdata = {
+ .init = mx27ads_sdhc2_init,
+ .exit = mx27ads_sdhc2_exit,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &mx27ads_nor_mtd_device,
+ &mxc_fec_device,
+ &mxc_w1_master_device,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+ {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ },
+};
+
+static void __init mx27ads_board_init(void)
+{
+ mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
+ "mx27ads");
+
+ mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+ mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
+ mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+ mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
+ mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
+ mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
+ mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
+
+ /* only the i2c master 1 is used on this CPU card */
+ i2c_register_board_info(1, mx27ads_i2c_devices,
+ ARRAY_SIZE(mx27ads_i2c_devices));
+ mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
+ mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
+ mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
+ mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx27ads_timer_init(void)
+{
+ unsigned long fref = 26000000;
+
+ if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
+ fref = 27000000;
+
+ mx27_clocks_init(fref);
+}
+
+static struct sys_timer mx27ads_timer = {
+ .init = mx27ads_timer_init,
+};
+
+static struct map_desc mx27ads_io_desc[] __initdata = {
+ {
+ .virtual = PBC_BASE_ADDRESS,
+ .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
+ .length = SZ_1M,
+ .type = MT_DEVICE,
+ },
+};
+
+static void __init mx27ads_map_io(void)
+{
+ mx27_map_io();
+ iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
+}
+
+MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
+ /* maintainer: Freescale Semiconductor, Inc. */
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27ads_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = mx27ads_board_init,
+ .timer = &mx27ads_timer,
+MACHINE_END
--- /dev/null
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <linux/gpio.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx27.h>
+#include <mach/mxc_nand.h>
+#include <mach/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <mach/imxfb.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+static unsigned int mxt_td60_pins[] __initdata = {
+ /* UART0 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* UART1 */
+ PE3_PF_UART2_CTS,
+ PE4_PF_UART2_RTS,
+ PE6_PF_UART2_TXD,
+ PE7_PF_UART2_RXD,
+ /* UART2 */
+ PE8_PF_UART3_TXD,
+ PE9_PF_UART3_RXD,
+ PE10_PF_UART3_CTS,
+ PE11_PF_UART3_RTS,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* I2C1 */
+ PD17_PF_I2C_DATA,
+ PD18_PF_I2C_CLK,
+ /* I2C2 */
+ PC5_PF_I2C2_SDA,
+ PC6_PF_I2C2_SCL,
+ /* FB */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA23_PF_LD17,
+ PA25_PF_CLS,
+ PA27_PF_SPL_SPR,
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ PA31_PF_OE_ACD,
+ /* OWIRE */
+ PE16_AF_OWIRE,
+ /* SDHC1*/
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+ PF8_AF_ATA_IORDY,
+ /* SDHC2*/
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+};
+
+static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static struct imxi2c_platform_data mxt_td60_i2c_data = {
+ .bitrate = 100000,
+};
+
+/* PCA9557 */
+static int mxt_td60_pca9557_setup(struct i2c_client *client,
+ unsigned gpio_base, unsigned ngpio,
+ void *context)
+{
+ static int mxt_td60_gpio_value[] = {
+ -1, -1, -1, -1, -1, -1, -1, 1
+ };
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
+ gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
+ if (mxt_td60_gpio_value[n] < 0)
+ gpio_direction_input(gpio_base + n);
+ else
+ gpio_direction_output(gpio_base + n,
+ mxt_td60_gpio_value[n]);
+ gpio_export(gpio_base + n, 0);
+ }
+
+ return 0;
+}
+
+static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
+ .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */
+ .invert = 0, /* Do not invert */
+ .setup = mxt_td60_pca9557_setup,
+};
+
+static struct i2c_board_info mxt_td60_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pca9557", 0x18),
+ .platform_data = &mxt_td60_pca9557_pdata,
+ },
+};
+
+static struct imxi2c_platform_data mxt_td60_i2c2_data = {
+ .bitrate = 100000,
+};
+
+static struct i2c_board_info mxt_td60_i2c2_devices[] = {
+};
+
+static struct imx_fb_videomode mxt_td60_modes[] = {
+ {
+ .mode = {
+ .name = "Chimei LW700AT9003",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 30303,
+ .hsync_len = 64,
+ .left_margin = 0x67,
+ .right_margin = 0x68,
+ .vsync_len = 16,
+ .upper_margin = 0x0f,
+ .lower_margin = 0x0f,
+ },
+ .bpp = 16,
+ .pcr = 0xFA208B83,
+ },
+};
+
+static struct imx_fb_platform_data mxt_td60_fb_data = {
+ .mode = mxt_td60_modes,
+ .num_modes = ARRAY_SIZE(mxt_td60_modes),
+
+ /*
+ * - HSYNC active high
+ * - VSYNC active high
+ * - clk notenabled while idle
+ * - clock inverted
+ * - data not inverted
+ * - data enable low active
+ * - enable sharp mode
+ */
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00020010,
+};
+
+static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
+ "sdhc1-card-detect", data);
+}
+
+static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOF(8), data);
+}
+
+static struct imxmmc_platform_data sdhc1_pdata = {
+ .init = mxt_td60_sdhc1_init,
+ .exit = mxt_td60_sdhc1_exit,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &mxc_fec_device,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+ {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ },
+};
+
+static void __init mxt_td60_board_init(void)
+{
+ mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
+ "MXT_TD60");
+
+ mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+ mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
+ mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+ mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
+
+ i2c_register_board_info(0, mxt_td60_i2c_devices,
+ ARRAY_SIZE(mxt_td60_i2c_devices));
+
+ i2c_register_board_info(1, mxt_td60_i2c2_devices,
+ ARRAY_SIZE(mxt_td60_i2c2_devices));
+
+ mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
+ mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
+ mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
+ mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mxt_td60_timer_init(void)
+{
+ mx27_clocks_init(26000000);
+}
+
+static struct sys_timer mxt_td60_timer = {
+ .init = mxt_td60_timer_init,
+};
+
+MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
+ /* maintainer: Maxtrack Industrial */
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = mxt_td60_board_init,
+ .timer = &mxt_td60_timer,
+MACHINE_END
+
--- /dev/null
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/dma-mapping.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx27.h>
+#include <mach/i2c.h>
+#include <asm/mach/time.h>
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+#include <mach/spi.h>
+#endif
+#include <mach/imx-uart.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
+#include <mach/mxc_nand.h>
+#include <mach/irqs.h>
+#include <mach/mmc.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices.h"
+
+#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
+#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
+
+static int pca100_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* SDHC */
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* SSI1 */
+ PC20_PF_SSI1_FS,
+ PC21_PF_SSI1_RXD,
+ PC22_PF_SSI1_TXD,
+ PC23_PF_SSI1_CLK,
+ /* onboard I2C */
+ PC5_PF_I2C2_SDA,
+ PC6_PF_I2C2_SCL,
+ /* external I2C */
+ PD17_PF_I2C_DATA,
+ PD18_PF_I2C_CLK,
+ /* SPI1 */
+ PD25_PF_CSPI1_RDY,
+ PD29_PF_CSPI1_SCLK,
+ PD30_PF_CSPI1_MISO,
+ PD31_PF_CSPI1_MOSI,
+ /* OTG */
+ OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+ PC7_PF_USBOTG_DATA5,
+ PC8_PF_USBOTG_DATA6,
+ PC9_PF_USBOTG_DATA0,
+ PC10_PF_USBOTG_DATA2,
+ PC11_PF_USBOTG_DATA1,
+ PC12_PF_USBOTG_DATA4,
+ PC13_PF_USBOTG_DATA3,
+ PE0_PF_USBOTG_NXT,
+ PE1_PF_USBOTG_STP,
+ PE2_PF_USBOTG_DIR,
+ PE24_PF_USBOTG_CLK,
+ PE25_PF_USBOTG_DATA7,
+ /* USBH2 */
+ USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+ PA0_PF_USBH2_CLK,
+ PA1_PF_USBH2_DIR,
+ PA2_PF_USBH2_DATA7,
+ PA3_PF_USBH2_NXT,
+ PA4_PF_USBH2_STP,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD21_AF_USBH2_DATA6,
+ PD22_AF_USBH2_DATA0,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD26_AF_USBH2_DATA5,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct mxc_nand_platform_data pca100_nand_board_info = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &mxc_w1_master_device,
+ &mxc_fec_device,
+ &mxc_wdt,
+};
+
+static struct imxi2c_platform_data pca100_i2c_1_data = {
+ .bitrate = 100000,
+};
+
+static struct at24_platform_data board_eeprom = {
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pca100_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+ .platform_data = &board_eeprom,
+ }, {
+ I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+ .type = "pcf8563"
+ }, {
+ I2C_BOARD_INFO("lm75", 0x4a),
+ .type = "lm75"
+ }
+};
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+static struct spi_eeprom at25320 = {
+ .name = "at25320an",
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = EE_ADDR2,
+};
+
+static struct spi_board_info pca100_spi_board_info[] __initdata = {
+ {
+ .modalias = "at25",
+ .max_speed_hz = 30000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .platform_data = &at25320,
+ },
+};
+
+static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+
+static struct spi_imx_master pca100_spi_0_data = {
+ .chipselect = pca100_spi_cs,
+ .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
+};
+#endif
+
+static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+ mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
+ gpio_set_value(GPIO_PORTC + 20, 1);
+ udelay(2);
+ gpio_set_value(GPIO_PORTC + 20, 0);
+ mxc_gpio_mode(PC20_PF_SSI1_FS);
+ msleep(2);
+}
+
+static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
+{
+ mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
+ gpio_set_value(GPIO_PORTC + 20, 0);
+ mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
+ gpio_set_value(GPIO_PORTC + 22, 0);
+ mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
+ gpio_set_value(GPIO_PORTC + 28, 0);
+ udelay(10);
+ gpio_set_value(GPIO_PORTC + 28, 1);
+ mxc_gpio_mode(PC20_PF_SSI1_FS);
+ mxc_gpio_mode(PC22_PF_SSI1_TXD);
+ msleep(2);
+}
+
+static struct imx_ssi_platform_data pca100_ssi_pdata = {
+ .ac97_reset = pca100_ac97_cold_reset,
+ .ac97_warm_reset = pca100_ac97_warm_reset,
+ .flags = IMX_SSI_USE_AC97,
+};
+
+static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = request_irq(IRQ_GPIOC(29), detect_irq,
+ IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+ "imx-mmc-detect", data);
+ if (ret)
+ printk(KERN_ERR
+ "pca100: Failed to reuest irq for sd/mmc detection\n");
+
+ return ret;
+}
+
+static void pca100_sdhc2_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOC(29), data);
+}
+
+static struct imxmmc_platform_data sdhc_pdata = {
+ .init = pca100_sdhc2_init,
+ .exit = pca100_sdhc2_exit,
+};
+
+static int otg_phy_init(struct platform_device *pdev)
+{
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+ return 0;
+}
+
+static struct mxc_usbh_platform_data otg_pdata = {
+ .init = otg_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static int usbh2_phy_init(struct platform_device *pdev)
+{
+ gpio_set_value(USBH2_PHY_CS_GPIO, 0);
+ return 0;
+}
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+ .init = usbh2_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init pca100_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", pca100_otg_mode);
+
+static void __init pca100_init(void)
+{
+ int ret;
+
+ /* SSI unit */
+ mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+ MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+ MXC_AUDMUX_V1_PCR_TFCSEL(3) |
+ MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+ MXC_AUDMUX_V1_PCR_RXDSEL(3));
+ mxc_audmux_v1_configure_port(3,
+ MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+ MXC_AUDMUX_V1_PCR_TFCSEL(0) |
+ MXC_AUDMUX_V1_PCR_TFSDIR |
+ MXC_AUDMUX_V1_PCR_RXDSEL(0));
+
+ ret = mxc_gpio_setup_multiple_pins(pca100_pins,
+ ARRAY_SIZE(pca100_pins), "PCA100");
+ if (ret)
+ printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
+
+ mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
+
+ mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+ mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
+ mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+
+ mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
+
+ /* only the i2c master 1 is used on this CPU card */
+ i2c_register_board_info(1, pca100_i2c_devices,
+ ARRAY_SIZE(pca100_i2c_devices));
+
+ mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
+
+ mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+ mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
+
+ /* GPIO0_IRQ */
+ mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
+ /* GPIO1_IRQ */
+ mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
+ /* GPIO2_IRQ */
+ mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+ spi_register_board_info(pca100_spi_board_info,
+ ARRAY_SIZE(pca100_spi_board_info));
+ mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+#endif
+
+ gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
+ gpio_direction_output(OTG_PHY_CS_GPIO, 1);
+ gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
+ gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
+
+#if defined(CONFIG_USB_ULPI)
+ if (otg_mode_host) {
+ otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+ mxc_register_device(&mxc_otg_host, &otg_pdata);
+ }
+
+ usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+ mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+ if (!otg_mode_host) {
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+ mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+ }
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init pca100_timer_init(void)
+{
+ mx27_clocks_init(26000000);
+}
+
+static struct sys_timer pca100_timer = {
+ .init = pca100_timer_init,
+};
+
+MACHINE_START(PCA100, "phyCARD-i.MX27")
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = pca100_init,
+ .timer = &pca100_timer,
+MACHINE_END
+
--- /dev/null
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/io.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/board-pcm038.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/iomux-mx27.h>
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+#include <mach/spi.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices.h"
+
+static int pcm038_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* UART2 */
+ PE3_PF_UART2_CTS,
+ PE4_PF_UART2_RTS,
+ PE6_PF_UART2_TXD,
+ PE7_PF_UART2_RXD,
+ /* UART3 */
+ PE8_PF_UART3_TXD,
+ PE9_PF_UART3_RXD,
+ PE10_PF_UART3_CTS,
+ PE11_PF_UART3_RTS,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* I2C2 */
+ PC5_PF_I2C2_SDA,
+ PC6_PF_I2C2_SCL,
+ /* SPI1 */
+ PD25_PF_CSPI1_RDY,
+ PD29_PF_CSPI1_SCLK,
+ PD30_PF_CSPI1_MISO,
+ PD31_PF_CSPI1_MOSI,
+ /* SSI1 */
+ PC20_PF_SSI1_FS,
+ PC21_PF_SSI1_RXD,
+ PC22_PF_SSI1_TXD,
+ PC23_PF_SSI1_CLK,
+ /* SSI4 */
+ PC16_PF_SSI4_FS,
+ PC17_PF_SSI4_RXD,
+ PC18_PF_SSI4_TXD,
+ PC19_PF_SSI4_CLK,
+ /* USB host */
+ PA0_PF_USBH2_CLK,
+ PA1_PF_USBH2_DIR,
+ PA2_PF_USBH2_DATA7,
+ PA3_PF_USBH2_NXT,
+ PA4_PF_USBH2_STP,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD21_AF_USBH2_DATA6,
+ PD22_AF_USBH2_DATA0,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD26_AF_USBH2_DATA5,
+};
+
+/*
+ * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
+ * 16 bit width
+ */
+
+static struct platdata_mtd_ram pcm038_sram_data = {
+ .bankwidth = 2,
+};
+
+static struct resource pcm038_sram_resource = {
+ .start = MX27_CS1_BASE_ADDR,
+ .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm038_sram_mtd_device = {
+ .name = "mtd-ram",
+ .id = 0,
+ .dev = {
+ .platform_data = &pcm038_sram_data,
+ },
+ .num_resources = 1,
+ .resource = &pcm038_sram_resource,
+};
+
+/*
+ * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
+ * 16 bit width
+ */
+static struct physmap_flash_data pcm038_flash_data = {
+ .width = 2,
+};
+
+static struct resource pcm038_flash_resource = {
+ .start = 0xc0000000,
+ .end = 0xc1ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm038_nor_mtd_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &pcm038_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &pcm038_flash_resource,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+ {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ }, {
+ .flags = IMXUART_HAVE_RTSCTS,
+ },
+};
+
+static struct mxc_nand_platform_data pcm038_nand_board_info = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &pcm038_nor_mtd_device,
+ &mxc_w1_master_device,
+ &mxc_fec_device,
+ &pcm038_sram_mtd_device,
+ &mxc_wdt,
+};
+
+/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
+ * setup other stuffs to access the sram. */
+static void __init pcm038_init_sram(void)
+{
+ mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
+}
+
+static struct imxi2c_platform_data pcm038_i2c_1_data = {
+ .bitrate = 100000,
+};
+
+static struct at24_platform_data board_eeprom = {
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pcm038_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+ .platform_data = &board_eeprom,
+ }, {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ }, {
+ I2C_BOARD_INFO("lm75", 0x4a),
+ }
+};
+
+static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
+
+static struct spi_imx_master pcm038_spi_0_data = {
+ .chipselect = pcm038_spi_cs,
+ .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
+};
+
+static struct regulator_consumer_supply sdhc1_consumers[] = {
+ {
+ .dev = &mxc_sdhc_device1.dev,
+ .supply = "sdhc_vcc",
+ },
+};
+
+static struct regulator_init_data sdhc1_data = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3400000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_FAST,
+ .always_on = 0,
+ .boot_on = 0,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
+ .consumer_supplies = sdhc1_consumers,
+};
+
+static struct regulator_consumer_supply cam_consumers[] = {
+ {
+ .dev = NULL,
+ .supply = "imx_cam_vcc",
+ },
+};
+
+static struct regulator_init_data cam_data = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3400000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_FAST,
+ .always_on = 0,
+ .boot_on = 0,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
+ .consumer_supplies = cam_consumers,
+};
+
+struct mc13783_regulator_init_data pcm038_regulators[] = {
+ {
+ .id = MC13783_REGU_VCAM,
+ .init_data = &cam_data,
+ }, {
+ .id = MC13783_REGU_VMMC1,
+ .init_data = &sdhc1_data,
+ },
+};
+
+static struct mc13783_platform_data pcm038_pmic = {
+ .regulators = pcm038_regulators,
+ .num_regulators = ARRAY_SIZE(pcm038_regulators),
+ .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR |
+ MC13783_USE_TOUCHSCREEN,
+};
+
+static struct spi_board_info pcm038_spi_board_info[] __initdata = {
+ {
+ .modalias = "mc13783",
+ .irq = IRQ_GPIOB(23),
+ .max_speed_hz = 300000,
+ .bus_num = 0,
+ .chip_select = 0,
+ .platform_data = &pcm038_pmic,
+ .mode = SPI_CS_HIGH,
+ }
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+ .portsc = MXC_EHCI_MODE_ULPI,
+ .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static void __init pcm038_init(void)
+{
+ mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
+ "PCM038");
+
+ pcm038_init_sram();
+
+ mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+ mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
+ mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+
+ mxc_gpio_mode(PE16_AF_OWIRE);
+ mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
+
+ /* only the i2c master 1 is used on this CPU card */
+ i2c_register_board_info(1, pcm038_i2c_devices,
+ ARRAY_SIZE(pcm038_i2c_devices));
+
+ mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+
+ /* PE18 for user-LED D40 */
+ mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
+
+ mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+
+ /* MC13783 IRQ */
+ mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
+
+ mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
+ spi_register_board_info(pcm038_spi_board_info,
+ ARRAY_SIZE(pcm038_spi_board_info));
+
+ mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#ifdef CONFIG_MACH_PCM970_BASEBOARD
+ pcm970_baseboard_init();
+#endif
+}
+
+static void __init pcm038_timer_init(void)
+{
+ mx27_clocks_init(26000000);
+}
+
+static struct sys_timer pcm038_timer = {
+ .init = pcm038_timer_init,
+};
+
+MACHINE_START(PCM038, "phyCORE-i.MX27")
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = pcm038_init,
+ .timer = &pcm038_timer,
+MACHINE_END
--- /dev/null
+/*
+ * arch/arm/mach-imx/mm-imx21.c
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/* MX21 memory map definition */
+static struct map_desc imx21_io_desc[] __initdata = {
+ /*
+ * this fixed mapping covers:
+ * - AIPI1
+ * - AIPI2
+ * - AITC
+ * - ROM Patch
+ * - and some reserved space
+ */
+ {
+ .virtual = MX21_AIPI_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
+ .length = MX21_AIPI_SIZE,
+ .type = MT_DEVICE
+ },
+ /*
+ * this fixed mapping covers:
+ * - CSI
+ * - ATA
+ */
+ {
+ .virtual = MX21_SAHB1_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
+ .length = MX21_SAHB1_SIZE,
+ .type = MT_DEVICE
+ },
+ /*
+ * this fixed mapping covers:
+ * - EMI
+ */
+ {
+ .virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
+ .length = MX21_X_MEMC_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+/*
+ * Initialize the memory map. It is called during the
+ * system startup to create static physical to virtual
+ * memory map for the IO modules.
+ */
+void __init mx21_map_io(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX21);
+ mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
+
+ iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
+}
+
+void __init mx21_init_irq(void)
+{
+ mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
+}
--- /dev/null
+/*
+ * arch/arm/mach-imx/mm-imx27.c
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/* MX27 memory map definition */
+static struct map_desc imx27_io_desc[] __initdata = {
+ /*
+ * this fixed mapping covers:
+ * - AIPI1
+ * - AIPI2
+ * - AITC
+ * - ROM Patch
+ * - and some reserved space
+ */
+ {
+ .virtual = MX27_AIPI_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
+ .length = MX27_AIPI_SIZE,
+ .type = MT_DEVICE
+ },
+ /*
+ * this fixed mapping covers:
+ * - CSI
+ * - ATA
+ */
+ {
+ .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
+ .length = MX27_SAHB1_SIZE,
+ .type = MT_DEVICE
+ },
+ /*
+ * this fixed mapping covers:
+ * - EMI
+ */
+ {
+ .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
+ .length = MX27_X_MEMC_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+/*
+ * Initialize the memory map. It is called during the
+ * system startup to create static physical to virtual
+ * memory map for the IO modules.
+ */
+void __init mx27_map_io(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX27);
+ mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+
+ iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
+}
+
+void __init mx27_init_irq(void)
+{
+ mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
+}
--- /dev/null
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/can/platform/sja1000.h>
+
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx27.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+static int pcm970_pins[] = {
+ /* SDHC */
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
+ /* display */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA23_PF_LD17,
+ PA24_PF_REV,
+ PA25_PF_CLS,
+ PA26_PF_PS,
+ PA27_PF_SPL_SPR,
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ PA31_PF_OE_ACD,
+ /*
+ * it seems the data line misses a pullup, so we must enable
+ * the internal pullup as a local workaround
+ */
+ PD17_PF_I2C_DATA | GPIO_PUEN,
+ PD18_PF_I2C_CLK,
+ /* Camera */
+ PB10_PF_CSI_D0,
+ PB11_PF_CSI_D1,
+ PB12_PF_CSI_D2,
+ PB13_PF_CSI_D3,
+ PB14_PF_CSI_D4,
+ PB15_PF_CSI_MCLK,
+ PB16_PF_CSI_PIXCLK,
+ PB17_PF_CSI_D5,
+ PB18_PF_CSI_D6,
+ PB19_PF_CSI_D7,
+ PB20_PF_CSI_VSYNC,
+ PB21_PF_CSI_HSYNC,
+};
+
+static int pcm970_sdhc2_get_ro(struct device *dev)
+{
+ return gpio_get_value(GPIO_PORTC + 28);
+}
+
+static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
+{
+ int ret;
+
+ ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
+ "imx-mmc-detect", data);
+ if (ret)
+ return ret;
+
+ ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
+ if (ret) {
+ free_irq(IRQ_GPIOC(29), data);
+ return ret;
+ }
+
+ gpio_direction_input(GPIO_PORTC + 28);
+
+ return 0;
+}
+
+static void pcm970_sdhc2_exit(struct device *dev, void *data)
+{
+ free_irq(IRQ_GPIOC(29), data);
+ gpio_free(GPIO_PORTC + 28);
+}
+
+static struct imxmmc_platform_data sdhc_pdata = {
+ .get_ro = pcm970_sdhc2_get_ro,
+ .init = pcm970_sdhc2_init,
+ .exit = pcm970_sdhc2_exit,
+};
+
+static struct imx_fb_videomode pcm970_modes[] = {
+ {
+ .mode = {
+ .name = "Sharp-LQ035Q7",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 188679, /* in ps (5.3MHz) */
+ .hsync_len = 7,
+ .left_margin = 5,
+ .right_margin = 16,
+ .vsync_len = 1,
+ .upper_margin = 7,
+ .lower_margin = 9,
+ },
+ /*
+ * - HSYNC active high
+ * - VSYNC active high
+ * - clk notenabled while idle
+ * - clock not inverted
+ * - data not inverted
+ * - data enable low active
+ * - enable sharp mode
+ */
+ .pcr = 0xF00080C0,
+ .bpp = 16,
+ }, {
+ .mode = {
+ .name = "TX090",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 38255,
+ .left_margin = 144,
+ .right_margin = 0,
+ .upper_margin = 7,
+ .lower_margin = 40,
+ .hsync_len = 96,
+ .vsync_len = 1,
+ },
+ /*
+ * - HSYNC active low (1 << 22)
+ * - VSYNC active low (1 << 23)
+ * - clk notenabled while idle
+ * - clock not inverted
+ * - data not inverted
+ * - data enable low active
+ * - enable sharp mode
+ */
+ .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
+ .bpp = 32,
+ },
+};
+
+static struct imx_fb_platform_data pcm038_fb_data = {
+ .mode = pcm970_modes,
+ .num_modes = ARRAY_SIZE(pcm970_modes),
+
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00020010,
+};
+
+static struct resource pcm970_sja1000_resources[] = {
+ {
+ .start = MX27_CS4_BASE_ADDR,
+ .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_GPIOE(19),
+ .end = IRQ_GPIOE(19),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+ },
+};
+
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+ .osc_freq = 16000000,
+ .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
+ .cdr = CDR_CBP,
+};
+
+static struct platform_device pcm970_sja1000 = {
+ .name = "sja1000_platform",
+ .dev = {
+ .platform_data = &pcm970_sja1000_platform_data,
+ },
+ .resource = pcm970_sja1000_resources,
+ .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
+
+/*
+ * system init for baseboard usage. Will be called by pcm038 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init pcm970_baseboard_init(void)
+{
+ mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
+ "PCM970");
+
+ mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
+ mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
+ mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+ platform_device_register(&pcm970_sja1000);
+}
--- /dev/null
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include "devices.h"
+
+static struct resource uart0[] = {
+ {
+ .start = MX2x_UART1_BASE_ADDR,
+ .end = MX2x_UART1_BASE_ADDR + 0x0B5,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_UART1,
+ .end = MX2x_INT_UART1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_uart_device0 = {
+ .name = "imx-uart",
+ .id = 0,
+ .resource = uart0,
+ .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+ {
+ .start = MX2x_UART2_BASE_ADDR,
+ .end = MX2x_UART2_BASE_ADDR + 0x0B5,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_UART2,
+ .end = MX2x_INT_UART2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_uart_device1 = {
+ .name = "imx-uart",
+ .id = 1,
+ .resource = uart1,
+ .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+ {
+ .start = MX2x_UART3_BASE_ADDR,
+ .end = MX2x_UART3_BASE_ADDR + 0x0B5,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_UART3,
+ .end = MX2x_INT_UART3,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_uart_device2 = {
+ .name = "imx-uart",
+ .id = 2,
+ .resource = uart2,
+ .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+ {
+ .start = MX2x_UART4_BASE_ADDR,
+ .end = MX2x_UART4_BASE_ADDR + 0x0B5,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_UART4,
+ .end = MX2x_INT_UART4,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_uart_device3 = {
+ .name = "imx-uart",
+ .id = 3,
+ .resource = uart3,
+ .num_resources = ARRAY_SIZE(uart3),
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource uart4[] = {
+ {
+ .start = MX27_UART5_BASE_ADDR,
+ .end = MX27_UART5_BASE_ADDR + 0x0B5,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_UART5,
+ .end = MX27_INT_UART5,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_uart_device4 = {
+ .name = "imx-uart",
+ .id = 4,
+ .resource = uart4,
+ .num_resources = ARRAY_SIZE(uart4),
+};
+
+static struct resource uart5[] = {
+ {
+ .start = MX27_UART6_BASE_ADDR,
+ .end = MX27_UART6_BASE_ADDR + 0x0B5,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_UART6,
+ .end = MX27_INT_UART6,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device mxc_uart_device5 = {
+ .name = "imx-uart",
+ .id = 5,
+ .resource = uart5,
+ .num_resources = ARRAY_SIZE(uart5),
+};
+#endif
+++ /dev/null
-if ARCH_MX2
-
-choice
- prompt "CPUs:"
- default MACH_MX21
-
-config MACH_MX21
- bool "i.MX21 support"
- select ARCH_MXC_AUDMUX_V1
- help
- This enables support for Freescale's MX2 based i.MX21 processor.
-
-config MACH_MX27
- bool "i.MX27 support"
- select ARCH_MXC_AUDMUX_V1
- help
- This enables support for Freescale's MX2 based i.MX27 processor.
-
-endchoice
-
-comment "MX2 platforms:"
-
-config MACH_MX21ADS
- bool "MX21ADS platform"
- depends on MACH_MX21
- help
- Include support for MX21ADS platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX27ADS
- bool "MX27ADS platform"
- depends on MACH_MX27
- help
- Include support for MX27ADS platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_PCM038
- bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
- depends on MACH_MX27
- select MXC_ULPI if USB_ULPI
- help
- Include support for phyCORE-i.MX27 (aka pcm038) platform. This
- includes specific configurations for the module and its peripherals.
-
-choice
- prompt "Baseboard"
- depends on MACH_PCM038
- default MACH_PCM970_BASEBOARD
-
-config MACH_PCM970_BASEBOARD
- prompt "PHYTEC PCM970 development board"
- bool
- help
- This adds board specific devices that can be found on Phytec's
- PCM970 evaluation board.
-
-endchoice
-
-config MACH_CPUIMX27
- bool "Eukrea CPUIMX27 module"
- depends on MACH_MX27
- help
- Include support for Eukrea CPUIMX27 platform. This includes
- specific configurations for the module and its peripherals.
-
-config MACH_EUKREA_CPUIMX27_USESDHC2
- bool "CPUIMX27 integrates SDHC2 module"
- depends on MACH_CPUIMX27
- help
- This adds support for the internal SDHC2 used on CPUIMX27 used
- for wifi or eMMC.
-
-choice
- prompt "Baseboard"
- depends on MACH_CPUIMX27
- default MACH_EUKREA_MBIMX27_BASEBOARD
-
-config MACH_EUKREA_MBIMX27_BASEBOARD
- prompt "Eukrea MBIMX27 development board"
- bool
- help
- This adds board specific devices that can be found on Eukrea's
- MBIMX27 evaluation board.
-
-endchoice
-
-config MACH_MX27_3DS
- bool "MX27PDK platform"
- depends on MACH_MX27
- help
- Include support for MX27PDK platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_IMX27LITE
- bool "LogicPD MX27 LITEKIT platform"
- depends on MACH_MX27
- help
- Include support for MX27 LITEKIT platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_PCA100
- bool "Phytec phyCARD-s (pca100)"
- depends on MACH_MX27
- select MXC_ULPI if USB_ULPI
- help
- Include support for phyCARD-s (aka pca100) platform. This
- includes specific configurations for the module and its peripherals.
-
-config MACH_MXT_TD60
- bool "Maxtrack i-MXT TD60"
- depends on MACH_MX27
- help
- Include support for i-MXT (aka td60) platform. This
- includes specific configurations for the module and its peripherals.
-
-endif
+++ /dev/null
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := devices.o serial.o
-
-obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
-
-obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
-obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
-
-obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
-obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
-obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
-obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
-obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
-obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
-obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
-obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
-obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
-obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
+++ /dev/null
-zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
-params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
-initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
-
-zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
-params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
-initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
+++ /dev/null
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/clkdev.h>
-#include <asm/div64.h>
-
-#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
-#define CCM_PCDR0 IO_ADDR_CCM(0x18)
-#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0 IO_ADDR_CCM(0x20)
-#define CCM_PCCR1 IO_ADDR_CCM(0x24)
-#define CCM_CCSR IO_ADDR_CCM(0x28)
-#define CCM_PMCTL IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_PRESC_OFFSET 29
-#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
-
-#define CCM_CSCR_USB_OFFSET 26
-#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
-#define CCM_CSCR_SD_OFFSET 24
-#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
-#define CCM_CSCR_SPLLRES (1 << 22)
-#define CCM_CSCR_MPLLRES (1 << 21)
-#define CCM_CSCR_SSI2_OFFSET 20
-#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
-#define CCM_CSCR_SSI1_OFFSET 19
-#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
-#define CCM_CSCR_FIR_OFFSET 18
-#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
-#define CCM_CSCR_SP (1 << 17)
-#define CCM_CSCR_MCU (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET 10
-#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
-#define CCM_CSCR_IPDIV_OFFSET 9
-#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
-
-#define CCM_CSCR_OSC26MDIV (1 << 4)
-#define CCM_CSCR_OSC26M (1 << 3)
-#define CCM_CSCR_FPM (1 << 2)
-#define CCM_CSCR_SPEN (1 << 1)
-#define CCM_CSCR_MPEN 1
-
-#define CCM_MPCTL0_CPLM (1 << 31)
-#define CCM_MPCTL0_PD_OFFSET 26
-#define CCM_MPCTL0_PD_MASK (0xf << 26)
-#define CCM_MPCTL0_MFD_OFFSET 16
-#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
-#define CCM_MPCTL0_MFI_OFFSET 10
-#define CCM_MPCTL0_MFI_MASK (0xf << 10)
-#define CCM_MPCTL0_MFN_OFFSET 0
-#define CCM_MPCTL0_MFN_MASK 0x3ff
-
-#define CCM_MPCTL1_LF (1 << 15)
-#define CCM_MPCTL1_BRMO (1 << 6)
-
-#define CCM_SPCTL0_CPLM (1 << 31)
-#define CCM_SPCTL0_PD_OFFSET 26
-#define CCM_SPCTL0_PD_MASK (0xf << 26)
-#define CCM_SPCTL0_MFD_OFFSET 16
-#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
-#define CCM_SPCTL0_MFI_OFFSET 10
-#define CCM_SPCTL0_MFI_MASK (0xf << 10)
-#define CCM_SPCTL0_MFN_OFFSET 0
-#define CCM_SPCTL0_MFN_MASK 0x3ff
-
-#define CCM_SPCTL1_LF (1 << 15)
-#define CCM_SPCTL1_BRMO (1 << 6)
-
-#define CCM_OSC26MCTL_PEAK_OFFSET 16
-#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
-#define CCM_OSC26MCTL_AGC_OFFSET 8
-#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
-#define CCM_OSC26MCTL_ANATEST_OFFSET 0
-#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
-
-#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
-#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
-#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
-#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
-#define CCM_PCDR0_NFCDIV_OFFSET 12
-#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
-#define CCM_PCDR0_48MDIV_OFFSET 5
-#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
-#define CCM_PCDR0_FIRIDIV_OFFSET 0
-#define CCM_PCDR0_FIRIDIV_MASK 0x1f
-#define CCM_PCDR1_PERDIV4_OFFSET 24
-#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
-#define CCM_PCDR1_PERDIV3_OFFSET 16
-#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
-#define CCM_PCDR1_PERDIV2_OFFSET 8
-#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
-#define CCM_PCDR1_PERDIV1_OFFSET 0
-#define CCM_PCDR1_PERDIV1_MASK 0x3f
-
-#define CCM_PCCR_HCLK_CSI_OFFSET 31
-#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_DMA_OFFSET 30
-#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_BROM_OFFSET 28
-#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_EMMA_OFFSET 27
-#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_LCDC_OFFSET 26
-#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
-#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
-#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
-#define CCM_PCCR_HCLK_BMI_OFFSET 23
-#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
-#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
-#define CCM_PCCR_PERCLK4_OFFSET 22
-#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
-#define CCM_PCCR_SLCDC_OFFSET 21
-#define CCM_PCCR_SLCDC_REG CCM_PCCR0
-#define CCM_PCCR_FIRI_BAUD_OFFSET 20
-#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
-#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
-#define CCM_PCCR_NFC_OFFSET 19
-#define CCM_PCCR_NFC_REG CCM_PCCR0
-#define CCM_PCCR_LCDC_OFFSET 18
-#define CCM_PCCR_LCDC_REG CCM_PCCR0
-#define CCM_PCCR_SSI1_BAUD_OFFSET 17
-#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
-#define CCM_PCCR_SSI2_BAUD_OFFSET 16
-#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
-#define CCM_PCCR_EMMA_OFFSET 15
-#define CCM_PCCR_EMMA_REG CCM_PCCR0
-#define CCM_PCCR_USBOTG_OFFSET 14
-#define CCM_PCCR_USBOTG_REG CCM_PCCR0
-#define CCM_PCCR_DMA_OFFSET 13
-#define CCM_PCCR_DMA_REG CCM_PCCR0
-#define CCM_PCCR_I2C1_OFFSET 12
-#define CCM_PCCR_I2C1_REG CCM_PCCR0
-#define CCM_PCCR_GPIO_OFFSET 11
-#define CCM_PCCR_GPIO_REG CCM_PCCR0
-#define CCM_PCCR_SDHC2_OFFSET 10
-#define CCM_PCCR_SDHC2_REG CCM_PCCR0
-#define CCM_PCCR_SDHC1_OFFSET 9
-#define CCM_PCCR_SDHC1_REG CCM_PCCR0
-#define CCM_PCCR_FIRI_OFFSET 8
-#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
-#define CCM_PCCR_FIRI_REG CCM_PCCR0
-#define CCM_PCCR_SSI2_IPG_OFFSET 7
-#define CCM_PCCR_SSI2_REG CCM_PCCR0
-#define CCM_PCCR_SSI1_IPG_OFFSET 6
-#define CCM_PCCR_SSI1_REG CCM_PCCR0
-#define CCM_PCCR_CSPI2_OFFSET 5
-#define CCM_PCCR_CSPI2_REG CCM_PCCR0
-#define CCM_PCCR_CSPI1_OFFSET 4
-#define CCM_PCCR_CSPI1_REG CCM_PCCR0
-#define CCM_PCCR_UART4_OFFSET 3
-#define CCM_PCCR_UART4_REG CCM_PCCR0
-#define CCM_PCCR_UART3_OFFSET 2
-#define CCM_PCCR_UART3_REG CCM_PCCR0
-#define CCM_PCCR_UART2_OFFSET 1
-#define CCM_PCCR_UART2_REG CCM_PCCR0
-#define CCM_PCCR_UART1_OFFSET 0
-#define CCM_PCCR_UART1_REG CCM_PCCR0
-
-#define CCM_PCCR_OWIRE_OFFSET 31
-#define CCM_PCCR_OWIRE_REG CCM_PCCR1
-#define CCM_PCCR_KPP_OFFSET 30
-#define CCM_PCCR_KPP_REG CCM_PCCR1
-#define CCM_PCCR_RTC_OFFSET 29
-#define CCM_PCCR_RTC_REG CCM_PCCR1
-#define CCM_PCCR_PWM_OFFSET 28
-#define CCM_PCCR_PWM_REG CCM_PCCR1
-#define CCM_PCCR_GPT3_OFFSET 27
-#define CCM_PCCR_GPT3_REG CCM_PCCR1
-#define CCM_PCCR_GPT2_OFFSET 26
-#define CCM_PCCR_GPT2_REG CCM_PCCR1
-#define CCM_PCCR_GPT1_OFFSET 25
-#define CCM_PCCR_GPT1_REG CCM_PCCR1
-#define CCM_PCCR_WDT_OFFSET 24
-#define CCM_PCCR_WDT_REG CCM_PCCR1
-#define CCM_PCCR_CSPI3_OFFSET 23
-#define CCM_PCCR_CSPI3_REG CCM_PCCR1
-
-#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
-#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
-#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
-#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
-#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
-#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
-#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
-#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
-#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
-#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
-#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
-#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
-#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
-#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
-#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
-#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
-#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
-#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
-#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
-#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
-#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
-#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
-#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
-#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
-#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
-#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
-#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
-#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
-#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
-#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
-#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
-#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
-#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
-#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
-#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
-#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
-#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
-
-#define CCM_CCSR_32KSR (1 << 15)
-
-#define CCM_CCSR_CLKMODE1 (1 << 9)
-#define CCM_CCSR_CLKMODE0 (1 << 8)
-
-#define CCM_CCSR_CLKOSEL_OFFSET 0
-#define CCM_CCSR_CLKOSEL_MASK 0x1f
-
-#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
-#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
-
-static int _clk_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= 1 << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
- return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(1 << clk->enable_shift);
- __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long _clk_generic_round_rate(struct clk *clk,
- unsigned long rate,
- u32 max_divisor)
-{
- u32 div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- div = parent_rate / rate;
- if (parent_rate % rate)
- div++;
-
- if (div > max_divisor)
- div = max_divisor;
-
- return parent_rate / div;
-}
-
-static int _clk_spll_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(CCM_CSCR);
- reg |= CCM_CSCR_SPEN;
- __raw_writel(reg, CCM_CSCR);
-
- while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
- ;
- return 0;
-}
-
-static void _clk_spll_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(CCM_CSCR);
- reg &= ~CCM_CSCR_SPEN;
- __raw_writel(reg, CCM_CSCR);
-}
-
-
-#define CSCR() (__raw_readl(CCM_CSCR))
-#define PCDR0() (__raw_readl(CCM_PCDR0))
-#define PCDR1() (__raw_readl(CCM_PCDR1))
-
-static unsigned long _clk_perclkx_round_rate(struct clk *clk,
- unsigned long rate)
-{
- return _clk_generic_round_rate(clk, rate, 64);
-}
-
-static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg;
- u32 div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (clk->id < 0 || clk->id > 3)
- return -EINVAL;
-
- div = parent_rate / rate;
- if (div > 64 || div < 1 || ((parent_rate / div) != rate))
- return -EINVAL;
- div--;
-
- reg =
- __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
- (clk->id << 3));
- reg |= div << (clk->id << 3);
- __raw_writel(reg, CCM_PCDR1);
-
- return 0;
-}
-
-static unsigned long _clk_usb_recalc(struct clk *clk)
-{
- unsigned long usb_pdf;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
-
- return parent_rate / (usb_pdf + 1U);
-}
-
-static unsigned long _clk_usb_round_rate(struct clk *clk,
- unsigned long rate)
-{
- return _clk_generic_round_rate(clk, rate, 8);
-}
-
-static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg;
- u32 div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- div = parent_rate / rate;
- if (div > 8 || div < 1 || ((parent_rate / div) != rate))
- return -EINVAL;
- div--;
-
- reg = CSCR() & ~CCM_CSCR_USB_MASK;
- reg |= div << CCM_CSCR_USB_OFFSET;
- __raw_writel(reg, CCM_CSCR);
-
- return 0;
-}
-
-static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
-{
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
-
- return 2UL * parent_rate / pdf;
-}
-
-static unsigned long _clk_ssi1_recalc(struct clk *clk)
-{
- return _clk_ssix_recalc(clk,
- (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
- >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
-}
-
-static unsigned long _clk_ssi2_recalc(struct clk *clk)
-{
- return _clk_ssix_recalc(clk,
- (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
- CCM_PCDR0_SSI2BAUDDIV_OFFSET);
-}
-
-static unsigned long _clk_nfc_recalc(struct clk *clk)
-{
- unsigned long nfc_pdf;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
- >> CCM_PCDR0_NFCDIV_OFFSET;
-
- return parent_rate / (nfc_pdf + 1);
-}
-
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->round_rate(clk->parent, rate);
-}
-
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
-{
- return clk->parent->set_rate(clk->parent, rate);
-}
-
-static unsigned long external_high_reference; /* in Hz */
-
-static unsigned long get_high_reference_clock_rate(struct clk *clk)
-{
- return external_high_reference;
-}
-
-/*
- * the high frequency external clock reference
- * Default case is 26MHz.
- */
-static struct clk ckih_clk = {
- .get_rate = get_high_reference_clock_rate,
-};
-
-static unsigned long external_low_reference; /* in Hz */
-
-static unsigned long get_low_reference_clock_rate(struct clk *clk)
-{
- return external_low_reference;
-}
-
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz.
- */
-static struct clk ckil_clk = {
- .get_rate = get_low_reference_clock_rate,
-};
-
-
-static unsigned long _clk_fpm_recalc(struct clk *clk)
-{
- return clk_get_rate(clk->parent) * 512;
-}
-
-/* Output of frequency pre multiplier */
-static struct clk fpm_clk = {
- .parent = &ckil_clk,
- .get_rate = _clk_fpm_recalc,
-};
-
-static unsigned long get_mpll_clk(struct clk *clk)
-{
- uint32_t reg;
- unsigned long ref_clk;
- unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
- unsigned long long temp;
-
- ref_clk = clk_get_rate(clk->parent);
-
- reg = __raw_readl(CCM_MPCTL0);
- pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
- mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
- mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
- mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
-
- mfi = (mfi <= 5) ? 5 : mfi;
- temp = 2LL * ref_clk * mfn;
- do_div(temp, mfd + 1);
- temp = 2LL * ref_clk * mfi + temp;
- do_div(temp, pdf + 1);
-
- return (unsigned long)temp;
-}
-
-static struct clk mpll_clk = {
- .parent = &ckih_clk,
- .get_rate = get_mpll_clk,
-};
-
-static unsigned long _clk_fclk_get_rate(struct clk *clk)
-{
- unsigned long parent_rate;
- u32 div;
-
- div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
- parent_rate = clk_get_rate(clk->parent);
-
- return parent_rate / (div+1);
-}
-
-static struct clk fclk_clk = {
- .parent = &mpll_clk,
- .get_rate = _clk_fclk_get_rate
-};
-
-static unsigned long get_spll_clk(struct clk *clk)
-{
- uint32_t reg;
- unsigned long ref_clk;
- unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
- unsigned long long temp;
-
- ref_clk = clk_get_rate(clk->parent);
-
- reg = __raw_readl(CCM_SPCTL0);
- pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
- mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
- mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
- mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
-
- mfi = (mfi <= 5) ? 5 : mfi;
- temp = 2LL * ref_clk * mfn;
- do_div(temp, mfd + 1);
- temp = 2LL * ref_clk * mfi + temp;
- do_div(temp, pdf + 1);
-
- return (unsigned long)temp;
-}
-
-static struct clk spll_clk = {
- .parent = &ckih_clk,
- .get_rate = get_spll_clk,
- .enable = _clk_spll_enable,
- .disable = _clk_spll_disable,
-};
-
-static unsigned long get_hclk_clk(struct clk *clk)
-{
- unsigned long rate;
- unsigned long bclk_pdf;
-
- bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
- >> CCM_CSCR_BCLK_OFFSET;
-
- rate = clk_get_rate(clk->parent);
- return rate / (bclk_pdf + 1);
-}
-
-static struct clk hclk_clk = {
- .parent = &fclk_clk,
- .get_rate = get_hclk_clk,
-};
-
-static unsigned long get_ipg_clk(struct clk *clk)
-{
- unsigned long rate;
- unsigned long ipg_pdf;
-
- ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
-
- rate = clk_get_rate(clk->parent);
- return rate / (ipg_pdf + 1);
-}
-
-static struct clk ipg_clk = {
- .parent = &hclk_clk,
- .get_rate = get_ipg_clk,
-};
-
-static unsigned long _clk_perclkx_recalc(struct clk *clk)
-{
- unsigned long perclk_pdf;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (clk->id < 0 || clk->id > 3)
- return 0;
-
- perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
-
- return parent_rate / (perclk_pdf + 1);
-}
-
-static struct clk per_clk[] = {
- {
- .id = 0,
- .parent = &mpll_clk,
- .get_rate = _clk_perclkx_recalc,
- }, {
- .id = 1,
- .parent = &mpll_clk,
- .get_rate = _clk_perclkx_recalc,
- }, {
- .id = 2,
- .parent = &mpll_clk,
- .round_rate = _clk_perclkx_round_rate,
- .set_rate = _clk_perclkx_set_rate,
- .get_rate = _clk_perclkx_recalc,
- /* Enable/Disable done via lcd_clkc[1] */
- }, {
- .id = 3,
- .parent = &mpll_clk,
- .round_rate = _clk_perclkx_round_rate,
- .set_rate = _clk_perclkx_set_rate,
- .get_rate = _clk_perclkx_recalc,
- /* Enable/Disable done via csi_clk[1] */
- },
-};
-
-static struct clk uart_ipg_clk[];
-
-static struct clk uart_clk[] = {
- {
- .id = 0,
- .parent = &per_clk[0],
- .secondary = &uart_ipg_clk[0],
- }, {
- .id = 1,
- .parent = &per_clk[0],
- .secondary = &uart_ipg_clk[1],
- }, {
- .id = 2,
- .parent = &per_clk[0],
- .secondary = &uart_ipg_clk[2],
- }, {
- .id = 3,
- .parent = &per_clk[0],
- .secondary = &uart_ipg_clk[3],
- },
-};
-
-static struct clk uart_ipg_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_UART1_REG,
- .enable_shift = CCM_PCCR_UART1_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_UART2_REG,
- .enable_shift = CCM_PCCR_UART2_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 2,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_UART3_REG,
- .enable_shift = CCM_PCCR_UART3_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 3,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_UART4_REG,
- .enable_shift = CCM_PCCR_UART4_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk gpt_ipg_clk[];
-
-static struct clk gpt_clk[] = {
- {
- .id = 0,
- .parent = &per_clk[0],
- .secondary = &gpt_ipg_clk[0],
- }, {
- .id = 1,
- .parent = &per_clk[0],
- .secondary = &gpt_ipg_clk[1],
- }, {
- .id = 2,
- .parent = &per_clk[0],
- .secondary = &gpt_ipg_clk[2],
- },
-};
-
-static struct clk gpt_ipg_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_GPT1_REG,
- .enable_shift = CCM_PCCR_GPT1_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_GPT2_REG,
- .enable_shift = CCM_PCCR_GPT2_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 2,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_GPT3_REG,
- .enable_shift = CCM_PCCR_GPT3_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk pwm_clk[] = {
- {
- .parent = &per_clk[0],
- .secondary = &pwm_clk[1],
- }, {
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_PWM_REG,
- .enable_shift = CCM_PCCR_PWM_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk sdhc_ipg_clk[];
-
-static struct clk sdhc_clk[] = {
- {
- .id = 0,
- .parent = &per_clk[1],
- .secondary = &sdhc_ipg_clk[0],
- }, {
- .id = 1,
- .parent = &per_clk[1],
- .secondary = &sdhc_ipg_clk[1],
- },
-};
-
-static struct clk sdhc_ipg_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SDHC1_REG,
- .enable_shift = CCM_PCCR_SDHC1_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SDHC2_REG,
- .enable_shift = CCM_PCCR_SDHC2_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk cspi_ipg_clk[];
-
-static struct clk cspi_clk[] = {
- {
- .id = 0,
- .parent = &per_clk[1],
- .secondary = &cspi_ipg_clk[0],
- }, {
- .id = 1,
- .parent = &per_clk[1],
- .secondary = &cspi_ipg_clk[1],
- }, {
- .id = 2,
- .parent = &per_clk[1],
- .secondary = &cspi_ipg_clk[2],
- },
-};
-
-static struct clk cspi_ipg_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_CSPI1_REG,
- .enable_shift = CCM_PCCR_CSPI1_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_CSPI2_REG,
- .enable_shift = CCM_PCCR_CSPI2_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 3,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_CSPI3_REG,
- .enable_shift = CCM_PCCR_CSPI3_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk lcdc_clk[] = {
- {
- .parent = &per_clk[2],
- .secondary = &lcdc_clk[1],
- .round_rate = _clk_parent_round_rate,
- .set_rate = _clk_parent_set_rate,
- }, {
- .parent = &ipg_clk,
- .secondary = &lcdc_clk[2],
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_LCDC_REG,
- .enable_shift = CCM_PCCR_LCDC_OFFSET,
- .disable = _clk_disable,
- }, {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
- .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk csi_clk[] = {
- {
- .parent = &per_clk[3],
- .secondary = &csi_clk[1],
- .round_rate = _clk_parent_round_rate,
- .set_rate = _clk_parent_set_rate,
- }, {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_CSI_REG,
- .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk usb_clk[] = {
- {
- .parent = &spll_clk,
- .secondary = &usb_clk[1],
- .get_rate = _clk_usb_recalc,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_USBOTG_REG,
- .enable_shift = CCM_PCCR_USBOTG_OFFSET,
- .disable = _clk_disable,
- .round_rate = _clk_usb_round_rate,
- .set_rate = _clk_usb_set_rate,
- }, {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
- .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
- .disable = _clk_disable,
- }
-};
-
-static struct clk ssi_ipg_clk[];
-
-static struct clk ssi_clk[] = {
- {
- .id = 0,
- .parent = &mpll_clk,
- .secondary = &ssi_ipg_clk[0],
- .get_rate = _clk_ssi1_recalc,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
- .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 1,
- .parent = &mpll_clk,
- .secondary = &ssi_ipg_clk[1],
- .get_rate = _clk_ssi2_recalc,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
- .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk ssi_ipg_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SSI1_REG,
- .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
- .disable = _clk_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SSI2_REG,
- .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-
-static struct clk nfc_clk = {
- .parent = &fclk_clk,
- .get_rate = _clk_nfc_recalc,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_NFC_REG,
- .enable_shift = CCM_PCCR_NFC_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk dma_clk[] = {
- {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_DMA_REG,
- .enable_shift = CCM_PCCR_DMA_OFFSET,
- .disable = _clk_disable,
- .secondary = &dma_clk[1],
- }, {
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_DMA_REG,
- .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
- .disable = _clk_disable,
- },
-};
-
-static struct clk brom_clk = {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_BROM_REG,
- .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk emma_clk[] = {
- {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_EMMA_REG,
- .enable_shift = CCM_PCCR_EMMA_OFFSET,
- .disable = _clk_disable,
- .secondary = &emma_clk[1],
- }, {
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
- .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
- .disable = _clk_disable,
- }
-};
-
-static struct clk slcdc_clk[] = {
- {
- .parent = &hclk_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_SLCDC_REG,
- .enable_shift = CCM_PCCR_SLCDC_OFFSET,
- .disable = _clk_disable,
- .secondary = &slcdc_clk[1],
- }, {
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
- .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
- .disable = _clk_disable,
- }
-};
-
-static struct clk wdog_clk = {
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_WDT_REG,
- .enable_shift = CCM_PCCR_WDT_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk gpio_clk = {
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_GPIO_REG,
- .enable_shift = CCM_PCCR_GPIO_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk i2c_clk = {
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_I2C1_REG,
- .enable_shift = CCM_PCCR_I2C1_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk kpp_clk = {
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_KPP_REG,
- .enable_shift = CCM_PCCR_KPP_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk owire_clk = {
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_OWIRE_REG,
- .enable_shift = CCM_PCCR_OWIRE_OFFSET,
- .disable = _clk_disable,
-};
-
-static struct clk rtc_clk = {
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = CCM_PCCR_RTC_REG,
- .enable_shift = CCM_PCCR_RTC_OFFSET,
- .disable = _clk_disable,
-};
-
-static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
-{
- return _clk_generic_round_rate(clk, rate, 8);
-}
-
-static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg;
- u32 div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- div = parent_rate / rate;
-
- if (div > 8 || div < 1 || ((parent_rate / div) != rate))
- return -EINVAL;
- div--;
-
- reg = __raw_readl(CCM_PCDR0);
-
- if (clk->parent == &usb_clk[0]) {
- reg &= ~CCM_PCDR0_48MDIV_MASK;
- reg |= div << CCM_PCDR0_48MDIV_OFFSET;
- }
- __raw_writel(reg, CCM_PCDR0);
-
- return 0;
-}
-
-static unsigned long _clk_clko_recalc(struct clk *clk)
-{
- u32 div = 0;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (clk->parent == &usb_clk[0]) /* 48M */
- div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
- >> CCM_PCDR0_48MDIV_OFFSET;
- div++;
-
- return parent_rate / div;
-}
-
-static struct clk clko_clk;
-
-static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 reg;
-
- reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
-
- if (parent == &ckil_clk)
- reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &fpm_clk)
- reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &ckih_clk)
- reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == mpll_clk.parent)
- reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == spll_clk.parent)
- reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &mpll_clk)
- reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &spll_clk)
- reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &fclk_clk)
- reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &hclk_clk)
- reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &ipg_clk)
- reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &per_clk[0])
- reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &per_clk[1])
- reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &per_clk[2])
- reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &per_clk[3])
- reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &ssi_clk[0])
- reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &ssi_clk[1])
- reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &nfc_clk)
- reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &usb_clk[0])
- reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
- else if (parent == &clko_clk)
- reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
- else
- return -EINVAL;
-
- __raw_writel(reg, CCM_CCSR);
-
- return 0;
-}
-
-static struct clk clko_clk = {
- .get_rate = _clk_clko_recalc,
- .set_rate = _clk_clko_set_rate,
- .round_rate = _clk_clko_round_rate,
- .set_parent = _clk_clko_set_parent,
-};
-
-
-#define _REGISTER_CLOCK(d, n, c) \
- { \
- .dev_id = d, \
- .con_id = n, \
- .clk = &c, \
- },
-static struct clk_lookup lookups[] = {
-/* It's unlikely that any driver wants one of them directly:
- _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
- _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
- _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
- _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
- _REGISTER_CLOCK(NULL, "spll", spll_clk)
- _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
- _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
- _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
-*/
- _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
- _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
- _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
- _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
- _REGISTER_CLOCK(NULL, "clko", clko_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
- _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
- _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
- _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3])
- _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
- _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
- _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
- _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
- _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
- _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
- _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
- _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
- _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
- _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
- _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
- _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
- _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
- _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
- _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
- _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
- _REGISTER_CLOCK(NULL, "brom", brom_clk)
- _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
- _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
- _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
- _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
- _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
- _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
- _REGISTER_CLOCK(NULL, "owire", owire_clk)
- _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
-};
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx21_clocks_init(unsigned long lref, unsigned long href)
-{
- u32 cscr;
-
- external_low_reference = lref;
- external_high_reference = href;
-
- /* detect clock reference for both system PLL */
- cscr = CSCR();
- if (cscr & CCM_CSCR_MCU)
- mpll_clk.parent = &ckih_clk;
- else
- mpll_clk.parent = &fpm_clk;
-
- if (cscr & CCM_CSCR_SP)
- spll_clk.parent = &ckih_clk;
- else
- spll_clk.parent = &fpm_clk;
-
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
- /* Turn off all clock gates */
- __raw_writel(0, CCM_PCCR0);
- __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
-
- /* This turns of the serial PLL as well */
- spll_clk.disable(&spll_clk);
-
- /* This will propagate to all children and init all the clock rates. */
- clk_enable(&per_clk[0]);
- clk_enable(&gpio_clk);
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
- clk_enable(&uart_clk[0]);
-#endif
-
- mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
- MX21_INT_GPT1);
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/module.h>
-
-#include <asm/clkdev.h>
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-
-#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
-
-/* Register offsets */
-#define CCM_CSCR IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
-#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
-#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
-#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
-#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
-#define CCM_PCDR0 IO_ADDR_CCM(0x18)
-#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
-#define CCM_PCCR0 IO_ADDR_CCM(0x20)
-#define CCM_PCCR1 IO_ADDR_CCM(0x24)
-#define CCM_CCSR IO_ADDR_CCM(0x28)
-#define CCM_PMCTL IO_ADDR_CCM(0x2c)
-#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
-#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
-
-#define CCM_CSCR_UPDATE_DIS (1 << 31)
-#define CCM_CSCR_SSI2 (1 << 23)
-#define CCM_CSCR_SSI1 (1 << 22)
-#define CCM_CSCR_VPU (1 << 21)
-#define CCM_CSCR_MSHC (1 << 20)
-#define CCM_CSCR_SPLLRES (1 << 19)
-#define CCM_CSCR_MPLLRES (1 << 18)
-#define CCM_CSCR_SP (1 << 17)
-#define CCM_CSCR_MCU (1 << 16)
-#define CCM_CSCR_OSC26MDIV (1 << 4)
-#define CCM_CSCR_OSC26M (1 << 3)
-#define CCM_CSCR_FPM (1 << 2)
-#define CCM_CSCR_SPEN (1 << 1)
-#define CCM_CSCR_MPEN (1 << 0)
-
-/* i.MX27 TO 2+ */
-#define CCM_CSCR_ARM_SRC (1 << 15)
-
-#define CCM_SPCTL1_LF (1 << 15)
-#define CCM_SPCTL1_BRMO (1 << 6)
-
-static struct clk mpll_main1_clk, mpll_main2_clk;
-
-static int clk_pccr_enable(struct clk *clk)
-{
- unsigned long reg;
-
- if (!clk->enable_reg)
- return 0;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= 1 << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
-
- return 0;
-}
-
-static void clk_pccr_disable(struct clk *clk)
-{
- unsigned long reg;
-
- if (!clk->enable_reg)
- return;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(1 << clk->enable_shift);
- __raw_writel(reg, clk->enable_reg);
-}
-
-static int clk_spll_enable(struct clk *clk)
-{
- unsigned long reg;
-
- reg = __raw_readl(CCM_CSCR);
- reg |= CCM_CSCR_SPEN;
- __raw_writel(reg, CCM_CSCR);
-
- while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
-
- return 0;
-}
-
-static void clk_spll_disable(struct clk *clk)
-{
- unsigned long reg;
-
- reg = __raw_readl(CCM_CSCR);
- reg &= ~CCM_CSCR_SPEN;
- __raw_writel(reg, CCM_CSCR);
-}
-
-static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
-{
- int cscr = __raw_readl(CCM_CSCR);
-
- if (clk->parent == parent)
- return 0;
-
- if (mx27_revision() >= CHIP_REV_2_0) {
- if (parent == &mpll_main1_clk) {
- cscr |= CCM_CSCR_ARM_SRC;
- } else {
- if (parent == &mpll_main2_clk)
- cscr &= ~CCM_CSCR_ARM_SRC;
- else
- return -EINVAL;
- }
- __raw_writel(cscr, CCM_CSCR);
- clk->parent = parent;
- return 0;
- }
- return -ENODEV;
-}
-
-static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
-{
- int div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- div = parent_rate / rate;
- if (parent_rate % rate)
- div++;
-
- if (div > 4)
- div = 4;
-
- return parent_rate / div;
-}
-
-static int set_rate_cpu(struct clk *clk, unsigned long rate)
-{
- unsigned int div;
- uint32_t reg;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- div = parent_rate / rate;
-
- if (div > 4 || div < 1 || ((parent_rate / div) != rate))
- return -EINVAL;
-
- div--;
-
- reg = __raw_readl(CCM_CSCR);
- if (mx27_revision() >= CHIP_REV_2_0) {
- reg &= ~(3 << 12);
- reg |= div << 12;
- reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
- __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
- } else {
- printk(KERN_ERR "Can't set CPU frequency!\n");
- }
-
- return 0;
-}
-
-static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
-{
- u32 div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- div = parent_rate / rate;
- if (parent_rate % rate)
- div++;
-
- if (div > 64)
- div = 64;
-
- return parent_rate / div;
-}
-
-static int set_rate_per(struct clk *clk, unsigned long rate)
-{
- u32 reg;
- u32 div;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (clk->id < 0 || clk->id > 3)
- return -EINVAL;
-
- div = parent_rate / rate;
- if (div > 64 || div < 1 || ((parent_rate / div) != rate))
- return -EINVAL;
- div--;
-
- reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
- reg |= div << (clk->id << 3);
- __raw_writel(reg, CCM_PCDR1);
-
- return 0;
-}
-
-static unsigned long get_rate_usb(struct clk *clk)
-{
- unsigned long usb_pdf;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
-
- return parent_rate / (usb_pdf + 1U);
-}
-
-static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
-{
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (mx27_revision() >= CHIP_REV_2_0)
- pdf += 4; /* MX27 TO2+ */
- else
- pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
-
- return 2UL * parent_rate / pdf;
-}
-
-static unsigned long get_rate_ssi1(struct clk *clk)
-{
- return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
-}
-
-static unsigned long get_rate_ssi2(struct clk *clk)
-{
- return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
- unsigned long nfc_pdf;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (mx27_revision() >= CHIP_REV_2_0)
- nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
- else
- nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
-
- return parent_rate / (nfc_pdf + 1);
-}
-
-static unsigned long get_rate_vpu(struct clk *clk)
-{
- unsigned long vpu_pdf;
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (mx27_revision() >= CHIP_REV_2_0) {
- vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
- vpu_pdf += 4;
- } else {
- vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
- vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
- }
-
- return 2UL * parent_rate / vpu_pdf;
-}
-
-static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
-{
- return clk->parent->round_rate(clk->parent, rate);
-}
-
-static unsigned long get_rate_parent(struct clk *clk)
-{
- return clk_get_rate(clk->parent);
-}
-
-static int set_rate_parent(struct clk *clk, unsigned long rate)
-{
- return clk->parent->set_rate(clk->parent, rate);
-}
-
-/* in Hz */
-static unsigned long external_high_reference = 26000000;
-
-static unsigned long get_rate_high_reference(struct clk *clk)
-{
- return external_high_reference;
-}
-
-/* in Hz */
-static unsigned long external_low_reference = 32768;
-
-static unsigned long get_rate_low_reference(struct clk *clk)
-{
- return external_low_reference;
-}
-
-static unsigned long get_rate_fpm(struct clk *clk)
-{
- return clk_get_rate(clk->parent) * 1024;
-}
-
-static unsigned long get_rate_mpll(struct clk *clk)
-{
- return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
- clk_get_rate(clk->parent));
-}
-
-static unsigned long get_rate_mpll_main(struct clk *clk)
-{
- unsigned long parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- /* i.MX27 TO2:
- * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
- * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
- */
- if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
- return 2UL * parent_rate / 3UL;
-
- return parent_rate;
-}
-
-static unsigned long get_rate_spll(struct clk *clk)
-{
- uint32_t reg;
- unsigned long rate;
-
- rate = clk_get_rate(clk->parent);
-
- reg = __raw_readl(CCM_SPCTL0);
-
- /* On TO2 we have to write the value back. Otherwise we
- * read 0 from this register the next time.
- */
- if (mx27_revision() >= CHIP_REV_2_0)
- __raw_writel(reg, CCM_SPCTL0);
-
- return mxc_decode_pll(reg, rate);
-}
-
-static unsigned long get_rate_cpu(struct clk *clk)
-{
- u32 div;
- unsigned long rate;
-
- if (mx27_revision() >= CHIP_REV_2_0)
- div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
- else
- div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
-
- rate = clk_get_rate(clk->parent);
- return rate / (div + 1);
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
- unsigned long rate, bclk_pdf;
-
- if (mx27_revision() >= CHIP_REV_2_0)
- bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
- else
- bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
-
- rate = clk_get_rate(clk->parent);
- return rate / (bclk_pdf + 1);
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
- unsigned long rate, ipg_pdf;
-
- if (mx27_revision() >= CHIP_REV_2_0)
- return clk_get_rate(clk->parent);
- else
- ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
-
- rate = clk_get_rate(clk->parent);
- return rate / (ipg_pdf + 1);
-}
-
-static unsigned long get_rate_per(struct clk *clk)
-{
- unsigned long perclk_pdf, parent_rate;
-
- parent_rate = clk_get_rate(clk->parent);
-
- if (clk->id < 0 || clk->id > 3)
- return 0;
-
- perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
-
- return parent_rate / (perclk_pdf + 1);
-}
-
-/*
- * the high frequency external clock reference
- * Default case is 26MHz. Could be changed at runtime
- * with a call to change_external_high_reference()
- */
-static struct clk ckih_clk = {
- .get_rate = get_rate_high_reference,
-};
-
-static struct clk mpll_clk = {
- .parent = &ckih_clk,
- .get_rate = get_rate_mpll,
-};
-
-/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
- * It provides the clock source whose rate is same as MPLL
- */
-static struct clk mpll_main1_clk = {
- .id = 0,
- .parent = &mpll_clk,
- .get_rate = get_rate_mpll_main,
-};
-
-/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
- * It provides the clock source whose rate is same MPLL * 2 / 3
- */
-static struct clk mpll_main2_clk = {
- .id = 1,
- .parent = &mpll_clk,
- .get_rate = get_rate_mpll_main,
-};
-
-static struct clk ahb_clk = {
- .parent = &mpll_main2_clk,
- .get_rate = get_rate_ahb,
-};
-
-static struct clk ipg_clk = {
- .parent = &ahb_clk,
- .get_rate = get_rate_ipg,
-};
-
-static struct clk cpu_clk = {
- .parent = &mpll_main2_clk,
- .set_parent = clk_cpu_set_parent,
- .round_rate = round_rate_cpu,
- .get_rate = get_rate_cpu,
- .set_rate = set_rate_cpu,
-};
-
-static struct clk spll_clk = {
- .parent = &ckih_clk,
- .get_rate = get_rate_spll,
- .enable = clk_spll_enable,
- .disable = clk_spll_disable,
-};
-
-/*
- * the low frequency external clock reference
- * Default case is 32.768kHz.
- */
-static struct clk ckil_clk = {
- .get_rate = get_rate_low_reference,
-};
-
-/* Output of frequency pre multiplier */
-static struct clk fpm_clk = {
- .parent = &ckil_clk,
- .get_rate = get_rate_fpm,
-};
-
-#define PCCR0 CCM_PCCR0
-#define PCCR1 CCM_PCCR1
-
-#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
- static struct clk name = { \
- .id = i, \
- .enable_reg = er, \
- .enable_shift = es, \
- .get_rate = gr, \
- .enable = clk_pccr_enable, \
- .disable = clk_pccr_disable, \
- .secondary = s, \
- .parent = p, \
- }
-
-#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
- static struct clk name = { \
- .id = i, \
- .enable_reg = er, \
- .enable_shift = es, \
- .get_rate = get_rate_##getsetround, \
- .set_rate = set_rate_##getsetround, \
- .round_rate = round_rate_##getsetround, \
- .enable = clk_pccr_enable, \
- .disable = clk_pccr_disable, \
- .secondary = s, \
- .parent = p, \
- }
-
-/* Forward declaration to keep the following list in order */
-static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
- dma_clk1, lcdc_clk2, vpu_clk1;
-
-/* All clocks we can gate through PCCRx in the order of PCCRx bits */
-DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk);
-DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk);
-DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk);
-DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
-DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
-DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
-DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
-DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk);
-
-DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk);
-DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk);
-DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
-DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
-DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
-DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk);
-DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
-DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
-
-/* Clocks we cannot directly gate, but drivers need their rates */
-DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk);
-DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk);
-DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk);
-DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk);
-DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk);
-DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk);
-DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk);
-DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk);
-DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk);
-DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk);
-DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk);
-DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk);
-DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk);
-DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk);
-DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk);
-DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk);
-DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk);
-DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk);
-DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
- { \
- .dev_id = d, \
- .con_id = n, \
- .clk = &c, \
- },
-
-static struct clk_lookup lookups[] = {
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
- _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
- _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
- _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
- _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
- _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
- _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
- _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
- _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
- _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
- _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
- _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
- _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
- _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
- _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
- _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
- _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
- _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
- _REGISTER_CLOCK(NULL, "csi", csi_clk)
- _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
- _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
- _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
- _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
- _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
- _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
- _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
- _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
- _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
- _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
- _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
- _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
- _REGISTER_CLOCK(NULL, "dma", dma_clk)
- _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
- _REGISTER_CLOCK(NULL, "brom", brom_clk)
- _REGISTER_CLOCK(NULL, "emma", emma_clk)
- _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
- _REGISTER_CLOCK(NULL, "emi", emi_clk)
- _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
- _REGISTER_CLOCK(NULL, "ata", ata_clk)
- _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
- _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
- _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
- _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
- _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
- _REGISTER_CLOCK(NULL, "iim", iim_clk)
- _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
- _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
- _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
- _REGISTER_CLOCK(NULL, "scc", scc_clk)
-};
-
-/* Adjust the clock path for TO2 and later */
-static void __init to2_adjust_clocks(void)
-{
- unsigned long cscr = __raw_readl(CCM_CSCR);
-
- if (mx27_revision() >= CHIP_REV_2_0) {
- if (cscr & CCM_CSCR_ARM_SRC)
- cpu_clk.parent = &mpll_main1_clk;
-
- if (!(cscr & CCM_CSCR_SSI2))
- ssi1_clk.parent = &spll_clk;
-
- if (!(cscr & CCM_CSCR_SSI1))
- ssi1_clk.parent = &spll_clk;
-
- if (!(cscr & CCM_CSCR_VPU))
- vpu_clk.parent = &spll_clk;
- } else {
- cpu_clk.parent = &mpll_clk;
- cpu_clk.set_parent = NULL;
- cpu_clk.round_rate = NULL;
- cpu_clk.set_rate = NULL;
- ahb_clk.parent = &mpll_clk;
-
- per1_clk.parent = &mpll_clk;
- per2_clk.parent = &mpll_clk;
- per3_clk.parent = &mpll_clk;
- per4_clk.parent = &mpll_clk;
-
- ssi1_clk.parent = &mpll_clk;
- ssi2_clk.parent = &mpll_clk;
-
- vpu_clk.parent = &mpll_clk;
- }
-}
-
-/*
- * must be called very early to get information about the
- * available clock rate when the timer framework starts
- */
-int __init mx27_clocks_init(unsigned long fref)
-{
- u32 cscr = __raw_readl(CCM_CSCR);
-
- external_high_reference = fref;
-
- /* detect clock reference for both system PLLs */
- if (cscr & CCM_CSCR_MCU)
- mpll_clk.parent = &ckih_clk;
- else
- mpll_clk.parent = &fpm_clk;
-
- if (cscr & CCM_CSCR_SP)
- spll_clk.parent = &ckih_clk;
- else
- spll_clk.parent = &fpm_clk;
-
- to2_adjust_clocks();
-
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
- /* Turn off all clocks we do not need */
- __raw_writel(0, CCM_PCCR0);
- __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
-
- spll_clk.disable(&spll_clk);
-
- /* enable basic clocks */
- clk_enable(&per1_clk);
- clk_enable(&gpio_clk);
- clk_enable(&emi_clk);
- clk_enable(&iim_clk);
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
- clk_enable(&uart1_clk);
-#endif
-
- mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
- MX27_INT_GPT1);
-
- return 0;
-}
-
+++ /dev/null
-/*
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-/*
- * i.MX27 specific CPU detection code
- */
-
-#include <linux/io.h>
-#include <linux/module.h>
-
-#include <mach/hardware.h>
-
-static int cpu_silicon_rev = -1;
-static int cpu_partnumber;
-
-#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
-
-static void query_silicon_parameter(void)
-{
- u32 val;
- /*
- * now we have access to the IO registers. As we need
- * the silicon revision very early we read it here to
- * avoid any further hooks
- */
- val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
- + SYS_CHIP_ID));
-
- cpu_silicon_rev = (int)(val >> 28);
- cpu_partnumber = (int)((val >> 12) & 0xFFFF);
-}
-
-/*
- * Returns:
- * the silicon revision of the cpu
- * -EINVAL - not a mx27
- */
-int mx27_revision(void)
-{
- if (cpu_silicon_rev == -1)
- query_silicon_parameter();
-
- if (cpu_partnumber != 0x8821)
- return -EINVAL;
-
- return cpu_silicon_rev;
-}
-EXPORT_SYMBOL(mx27_revision);
+++ /dev/null
-/*
- * Author: MontaVista Software, Inc.
- * <source@mvista.com>
- *
- * Based on the OMAP devices.c
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/dma-mapping.h>
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/mmc.h>
-
-#include "devices.h"
-
-/*
- * SPI master controller
- *
- * - i.MX1: 2 channel (slighly different register setting)
- * - i.MX21: 2 channel
- * - i.MX27: 3 channel
- */
-#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
- static struct resource mxc_spi_resources ## n[] = { \
- { \
- .start = baseaddr, \
- .end = baseaddr + SZ_4K - 1, \
- .flags = IORESOURCE_MEM, \
- }, { \
- .start = irq, \
- .end = irq, \
- .flags = IORESOURCE_IRQ, \
- }, \
- }; \
- \
- struct platform_device mxc_spi_device ## n = { \
- .name = "spi_imx", \
- .id = n, \
- .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
- .resource = mxc_spi_resources ## n, \
- }
-
-DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
-DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
-#endif
-
-/*
- * General Purpose Timer
- * - i.MX21: 3 timers
- * - i.MX27: 6 timers
- */
-#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
- static struct resource timer ## n ##_resources[] = { \
- { \
- .start = baseaddr, \
- .end = baseaddr + SZ_4K - 1, \
- .flags = IORESOURCE_MEM, \
- }, { \
- .start = irq, \
- .end = irq, \
- .flags = IORESOURCE_IRQ, \
- } \
- }; \
- \
- struct platform_device mxc_gpt ## n = { \
- .name = "imx_gpt", \
- .id = n, \
- .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
- .resource = timer ## n ## _resources, \
- }
-
-/* We use gpt1 as system timer, so do not add a device for this one */
-DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
-DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
-DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
-DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
-#endif
-
-/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
-static struct resource mxc_wdt_resources[] = {
- {
- .start = MX2x_WDOG_BASE_ADDR,
- .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device mxc_wdt = {
- .name = "imx2-wdt",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_wdt_resources),
- .resource = mxc_wdt_resources,
-};
-
-static struct resource mxc_w1_master_resources[] = {
- {
- .start = MX2x_OWIRE_BASE_ADDR,
- .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device mxc_w1_master_device = {
- .name = "mxc_w1",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
- .resource = mxc_w1_master_resources,
-};
-
-#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
- static struct resource pfx ## _nand_resources[] = { \
- { \
- .start = baseaddr, \
- .end = baseaddr + SZ_4K - 1, \
- .flags = IORESOURCE_MEM, \
- }, { \
- .start = irq, \
- .end = irq, \
- .flags = IORESOURCE_IRQ, \
- }, \
- }; \
- \
- struct platform_device pfx ## _nand_device = { \
- .name = "mxc_nand", \
- .id = 0, \
- .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
- .resource = pfx ## _nand_resources, \
- }
-
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
-#endif
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
-#endif
-
-/*
- * lcdc:
- * - i.MX1: the basic controller
- * - i.MX21: to be checked
- * - i.MX27: like i.MX1, with slightly variations
- */
-static struct resource mxc_fb[] = {
- {
- .start = MX2x_LCDC_BASE_ADDR,
- .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX2x_INT_LCDC,
- .end = MX2x_INT_LCDC,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* mxc lcd driver */
-struct platform_device mxc_fb_device = {
- .name = "imx-fb",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_fb),
- .resource = mxc_fb,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-#ifdef CONFIG_MACH_MX27
-static struct resource mxc_fec_resources[] = {
- {
- .start = MX27_FEC_BASE_ADDR,
- .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX27_INT_FEC,
- .end = MX27_INT_FEC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_fec_device = {
- .name = "fec",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_fec_resources),
- .resource = mxc_fec_resources,
-};
-#endif
-
-#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
- static struct resource mxc_i2c_resources ## n[] = { \
- { \
- .start = baseaddr, \
- .end = baseaddr + SZ_4K - 1, \
- .flags = IORESOURCE_MEM, \
- }, { \
- .start = irq, \
- .end = irq, \
- .flags = IORESOURCE_IRQ, \
- } \
- }; \
- \
- struct platform_device mxc_i2c_device ## n = { \
- .name = "imx-i2c", \
- .id = n, \
- .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
- .resource = mxc_i2c_resources ## n, \
- }
-
-DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
-#endif
-
-static struct resource mxc_pwm_resources[] = {
- {
- .start = MX2x_PWM_BASE_ADDR,
- .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX2x_INT_PWM,
- .end = MX2x_INT_PWM,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-struct platform_device mxc_pwm_device = {
- .name = "mxc_pwm",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_pwm_resources),
- .resource = mxc_pwm_resources,
-};
-
-#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
- static struct resource mxc_sdhc_resources ## n[] = { \
- { \
- .start = baseaddr, \
- .end = baseaddr + SZ_4K - 1, \
- .flags = IORESOURCE_MEM, \
- }, { \
- .start = irq, \
- .end = irq, \
- .flags = IORESOURCE_IRQ, \
- }, { \
- .start = dmareq, \
- .end = dmareq, \
- .flags = IORESOURCE_DMA, \
- }, \
- }; \
- \
- static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
- \
- struct platform_device mxc_sdhc_device ## n = { \
- .name = "mxc-mmc", \
- .id = n, \
- .dev = { \
- .dma_mask = &mxc_sdhc ## n ## _dmamask, \
- .coherent_dma_mask = DMA_BIT_MASK(32), \
- }, \
- .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
- .resource = mxc_sdhc_resources ## n, \
- }
-
-DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
-DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
-
-#ifdef CONFIG_MACH_MX27
-static struct resource otg_resources[] = {
- {
- .start = MX27_USBOTG_BASE_ADDR,
- .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX27_INT_USB3,
- .end = MX27_INT_USB3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static u64 otg_dmamask = DMA_BIT_MASK(32);
-
-/* OTG gadget device */
-struct platform_device mxc_otg_udc_device = {
- .name = "fsl-usb2-udc",
- .id = -1,
- .dev = {
- .dma_mask = &otg_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = otg_resources,
- .num_resources = ARRAY_SIZE(otg_resources),
-};
-
-/* OTG host */
-struct platform_device mxc_otg_host = {
- .name = "mxc-ehci",
- .id = 0,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .dma_mask = &otg_dmamask,
- },
- .resource = otg_resources,
- .num_resources = ARRAY_SIZE(otg_resources),
-};
-
-/* USB host 1 */
-
-static u64 usbh1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource mxc_usbh1_resources[] = {
- {
- .start = MX27_USBOTG_BASE_ADDR + 0x200,
- .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX27_INT_USB1,
- .end = MX27_INT_USB1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_usbh1 = {
- .name = "mxc-ehci",
- .id = 1,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .dma_mask = &usbh1_dmamask,
- },
- .resource = mxc_usbh1_resources,
- .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
-};
-
-/* USB host 2 */
-static u64 usbh2_dmamask = DMA_BIT_MASK(32);
-
-static struct resource mxc_usbh2_resources[] = {
- {
- .start = MX27_USBOTG_BASE_ADDR + 0x400,
- .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX27_INT_USB2,
- .end = MX27_INT_USB2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_usbh2 = {
- .name = "mxc-ehci",
- .id = 2,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .dma_mask = &usbh2_dmamask,
- },
- .resource = mxc_usbh2_resources,
- .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
-};
-#endif
-
-#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
- { \
- .name = _name, \
- .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
- .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
- .flags = IORESOURCE_DMA, \
- }
-
-#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
- static struct resource imx_ssi_resources ## n[] = { \
- { \
- .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
- .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
- .flags = IORESOURCE_MEM, \
- }, { \
- .start = MX2x_INT_SSI1, \
- .end = MX2x_INT_SSI1, \
- .flags = IORESOURCE_IRQ, \
- }, \
- DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
- DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
- DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
- DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
- }; \
- \
- struct platform_device imx_ssi_device ## n = { \
- .name = "imx-ssi", \
- .id = n, \
- .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
- .resource = imx_ssi_resources ## n, \
- }
-
-DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
-DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
-
-/* GPIO port description */
-#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
- { \
- .chip.label = "gpio-" #n, \
- .irq = _irq, \
- .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
- n * 0x100), \
- .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
- }
-
-#define DEFINE_MXC_GPIO_PORT(SOC, n) \
- { \
- .chip.label = "gpio-" #n, \
- .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
- n * 0x100), \
- .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
- }
-
-#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
- static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
- DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
- DEFINE_MXC_GPIO_PORT(SOC, 1), \
- DEFINE_MXC_GPIO_PORT(SOC, 2), \
- DEFINE_MXC_GPIO_PORT(SOC, 3), \
- DEFINE_MXC_GPIO_PORT(SOC, 4), \
- DEFINE_MXC_GPIO_PORT(SOC, 5), \
- }
-
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_GPIO_PORTS(MX21, imx21);
-#endif
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_GPIO_PORTS(MX27, imx27);
-#endif
-
-int __init mxc_register_gpios(void)
-{
-#ifdef CONFIG_MACH_MX21
- if (cpu_is_mx21())
- return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
- else
-#endif
-#ifdef CONFIG_MACH_MX27
- if (cpu_is_mx27())
- return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
- else
-#endif
- return 0;
-}
-
-#ifdef CONFIG_MACH_MX21
-static struct resource mx21_usbhc_resources[] = {
- {
- .start = MX21_USBOTG_BASE_ADDR,
- .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = MX21_INT_USBHOST,
- .end = MX21_INT_USBHOST,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mx21_usbhc_device = {
- .name = "imx21-hcd",
- .id = 0,
- .dev = {
- .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
- .resource = mx21_usbhc_resources,
-};
-#endif
-
+++ /dev/null
-extern struct platform_device mxc_gpt1;
-extern struct platform_device mxc_gpt2;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_gpt3;
-extern struct platform_device mxc_gpt4;
-extern struct platform_device mxc_gpt5;
-#endif
-extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
-extern struct platform_device mxc_uart_device5;
-extern struct platform_device mxc_w1_master_device;
-#ifdef CONFIG_MACH_MX21
-extern struct platform_device imx21_nand_device;
-#endif
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device imx27_nand_device;
-#endif
-extern struct platform_device mxc_fb_device;
-extern struct platform_device mxc_fec_device;
-extern struct platform_device mxc_pwm_device;
-extern struct platform_device mxc_i2c_device0;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_i2c_device1;
-#endif
-extern struct platform_device mxc_sdhc_device0;
-extern struct platform_device mxc_sdhc_device1;
-extern struct platform_device mxc_otg_udc_device;
-extern struct platform_device mxc_otg_host;
-extern struct platform_device mxc_usbh1;
-extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_spi_device2;
-#endif
-extern struct platform_device mx21_usbhc_device;
-extern struct platform_device imx_ssi_device0;
-extern struct platform_device imx_ssi_device1;
+++ /dev/null
-/*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx27.h>
-#include <mach/imxfb.h>
-#include <mach/hardware.h>
-#include <mach/mmc.h>
-#include <mach/imx-uart.h>
-
-#include "devices.h"
-
-static int eukrea_mbimx27_pins[] = {
- /* UART2 */
- PE3_PF_UART2_CTS,
- PE4_PF_UART2_RTS,
- PE6_PF_UART2_TXD,
- PE7_PF_UART2_RXD,
- /* UART3 */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
- PE10_PF_UART3_CTS,
- PE11_PF_UART3_RTS,
- /* UART4 */
- PB26_AF_UART4_RTS,
- PB28_AF_UART4_TXD,
- PB29_AF_UART4_CTS,
- PB31_AF_UART4_RXD,
- /* SDHC1*/
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
- /* display */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
- /* SPI1 */
- PD28_PF_CSPI1_SS0,
- PD29_PF_CSPI1_SCLK,
- PD30_PF_CSPI1_MISO,
- PD31_PF_CSPI1_MOSI,
-};
-
-static struct gpio_led gpio_leds[] = {
- {
- .name = "led1",
- .default_trigger = "heartbeat",
- .active_low = 1,
- .gpio = GPIO_PORTF | 16,
- },
- {
- .name = "led2",
- .default_trigger = "none",
- .active_low = 1,
- .gpio = GPIO_PORTF | 19,
- },
- {
- .name = "backlight",
- .default_trigger = "backlight",
- .active_low = 0,
- .gpio = GPIO_PORTE | 5,
- },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- },
-};
-
-static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
- {
- .mode = {
- .name = "CMO-QGVA",
- .refresh = 60,
- .xres = 320,
- .yres = 240,
- .pixclock = 156000,
- .hsync_len = 30,
- .left_margin = 38,
- .right_margin = 20,
- .vsync_len = 3,
- .upper_margin = 15,
- .lower_margin = 4,
- },
- .pcr = 0xFAD08B80,
- .bpp = 16,
- },
-};
-
-static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
- .mode = eukrea_mbimx27_modes,
- .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
-
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00040060,
-};
-
-static struct imxuart_platform_data uart_pdata[] = {
- {
- .flags = IMXUART_HAVE_RTSCTS,
- },
- {
- .flags = IMXUART_HAVE_RTSCTS,
- },
-};
-
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
- || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-
-#define ADS7846_PENDOWN (GPIO_PORTD | 25)
-
-static void ads7846_dev_init(void)
-{
- if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
- printk(KERN_ERR "can't get ads746 pen down GPIO\n");
- return;
- }
-
- gpio_direction_input(ADS7846_PENDOWN);
-}
-
-static int ads7846_get_pendown_state(void)
-{
- return !gpio_get_value(ADS7846_PENDOWN);
-}
-
-static struct ads7846_platform_data ads7846_config __initdata = {
- .get_pendown_state = ads7846_get_pendown_state,
- .keep_vref_on = 1,
-};
-
-static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
- [0] = {
- .modalias = "ads7846",
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 1500000,
- .irq = IRQ_GPIOD(25),
- .platform_data = &ads7846_config,
- .mode = SPI_MODE_2,
- },
-};
-
-static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
-
-static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
- .chipselect = eukrea_mbimx27_spi_cs,
- .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
-};
-#endif
-
-static struct platform_device *platform_devices[] __initdata = {
- &leds_gpio,
-};
-
-/*
- * system init for baseboard usage. Will be called by cpuimx27 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimx27_baseboard_init(void)
-{
- mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
- ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
-
- mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
- mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
-
- mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
- mxc_register_device(&mxc_sdhc_device0, NULL);
-
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
- || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- /* SPI and ADS7846 Touchscreen controler init */
- mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
- mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
- mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
- spi_register_board_info(eukrea_mbimx27_spi_board_info,
- ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
- ads7846_dev_init();
-#endif
-
- /* Leds configuration */
- mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
- mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
- /* Backlight */
- mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
+++ /dev/null
-/*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
- *
- * Based on pcm038.c which is :
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/i2c.h>
-#include <linux/io.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/board-eukrea_cpuimx27.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
-#include <mach/mxc_nand.h>
-
-#include "devices.h"
-
-static int eukrea_cpuimx27_pins[] = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* UART4 */
- PB26_AF_UART4_RTS,
- PB28_AF_UART4_TXD,
- PB29_AF_UART4_CTS,
- PB31_AF_UART4_RXD,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* I2C1 */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
- /* SDHC2 */
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
- /* Quad UART's IRQ */
- GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
- GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
- GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
- GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
-#endif
-};
-
-static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
- .width = 2,
-};
-
-static struct resource eukrea_cpuimx27_flash_resource = {
- .start = 0xc0000000,
- .end = 0xc3ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &eukrea_cpuimx27_flash_data,
- },
- .num_resources = 1,
- .resource = &eukrea_cpuimx27_flash_resource,
-};
-
-static struct imxuart_platform_data uart_pdata[] = {
- {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- },
-};
-
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &eukrea_cpuimx27_nor_mtd_device,
- &mxc_fec_device,
-};
-
-static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
- .bitrate = 100000,
-};
-
-static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
- {
- I2C_BOARD_INFO("pcf8563", 0x51),
- },
-};
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
- .irq = IRQ_GPIOB(23),
- .uartclk = 14745600,
- .regshift = 1,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
- }, {
- .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
- .irq = IRQ_GPIOB(22),
- .uartclk = 14745600,
- .regshift = 1,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
- }, {
- .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
- .irq = IRQ_GPIOB(27),
- .uartclk = 14745600,
- .regshift = 1,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
- }, {
- .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
- .irq = IRQ_GPIOB(30),
- .uartclk = 14745600,
- .regshift = 1,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
- }, {
- }
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = serial_platform_data,
- },
-};
-#endif
-
-static void __init eukrea_cpuimx27_init(void)
-{
- mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
- ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
-
- mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-
- mxc_register_device(&imx27_nand_device,
- &eukrea_cpuimx27_nand_board_info);
-
- i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
- ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
-
- mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
- /* SDHC2 can be used for Wifi */
- mxc_register_device(&mxc_sdhc_device1, NULL);
- /* in which case UART4 is also used for Bluetooth */
- mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
-#endif
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
- platform_device_register(&serial_device);
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
- eukrea_mbimx27_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx27_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-static struct sys_timer eukrea_cpuimx27_timer = {
- .init = eukrea_cpuimx27_timer_init,
-};
-
-MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = eukrea_cpuimx27_init,
- .timer = &eukrea_cpuimx27_timer,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx27.h>
-
-#include "devices.h"
-
-static unsigned int mx27lite_pins[] = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
-};
-
-static struct imxuart_platform_data uart_pdata = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mxc_fec_device,
-};
-
-static void __init mx27lite_init(void)
-{
- mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
- "imx27lite");
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init mx27lite_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-static struct sys_timer mx27lite_timer = {
- .init = mx27lite_timer_init,
-};
-
-MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = mx27lite_init,
- .timer = &mx27lite_timer,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/gpio.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <mach/imx-uart.h>
-#include <mach/imxfb.h>
-#include <mach/iomux-mx21.h>
-#include <mach/mxc_nand.h>
-#include <mach/mmc.h>
-
-#include "devices.h"
-
-/*
- * Memory-mapped I/O on MX21ADS base board
- */
-#define MX21ADS_MMIO_BASE_ADDR 0xf5000000
-#define MX21ADS_MMIO_SIZE SZ_16M
-
-#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
- (MX21ADS_MMIO_BASE_ADDR + (offset))
-
-#define MX21ADS_CS8900A_IRQ IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG MX21ADS_REG_ADDR(0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
-#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
-#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP 0x0001 /* read */
-#define MX21ADS_IO_TP6 0x0001 /* write */
-#define MX21ADS_IO_SW_SEL 0x0002 /* read */
-#define MX21ADS_IO_TP7 0x0002 /* write */
-#define MX21ADS_IO_RESET_E_UART 0x0004
-#define MX21ADS_IO_RESET_BASE 0x0008
-#define MX21ADS_IO_CSI_CTL2 0x0010
-#define MX21ADS_IO_CSI_CTL1 0x0020
-#define MX21ADS_IO_CSI_CTL0 0x0040
-#define MX21ADS_IO_UART1_EN 0x0080
-#define MX21ADS_IO_UART4_EN 0x0100
-#define MX21ADS_IO_LCDON 0x0200
-#define MX21ADS_IO_IRDA_EN 0x0400
-#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
-#define MX21ADS_IO_IRDA_MD0_B 0x1000
-#define MX21ADS_IO_IRDA_MD1 0x2000
-#define MX21ADS_IO_LED4_ON 0x4000
-#define MX21ADS_IO_LED3_ON 0x8000
-
-static unsigned int mx21ads_pins[] = {
-
- /* CS8900A */
- (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
-
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
-
- /* UART3 (IrDA) - only TXD and RXD */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
-
- /* UART4 */
- PB26_AF_UART4_RTS,
- PB28_AF_UART4_TXD,
- PB29_AF_UART4_CTS,
- PB31_AF_UART4_RXD,
-
- /* LCDC */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA24_PF_REV, /* Sharp panel dedicated signal */
- PA25_PF_CLS, /* Sharp panel dedicated signal */
- PA26_PF_PS, /* Sharp panel dedicated signal */
- PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
-
- /* MMC/SDHC */
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
-
- /* NFC */
- PF0_PF_NRFB,
- PF1_PF_NFCE,
- PF2_PF_NFWP,
- PF3_PF_NFCLE,
- PF4_PF_NFALE,
- PF5_PF_NFRE,
- PF6_PF_NFWE,
- PF7_PF_NFIO0,
- PF8_PF_NFIO1,
- PF9_PF_NFIO2,
- PF10_PF_NFIO3,
- PF11_PF_NFIO4,
- PF12_PF_NFIO5,
- PF13_PF_NFIO6,
- PF14_PF_NFIO7,
-};
-
-/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
-static struct physmap_flash_data mx21ads_flash_data = {
- .width = 4,
-};
-
-static struct resource mx21ads_flash_resource = {
- .start = MX21_CS0_BASE_ADDR,
- .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mx21ads_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx21ads_flash_data,
- },
- .num_resources = 1,
- .resource = &mx21ads_flash_resource,
-};
-
-static struct imxuart_platform_data uart_pdata = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct imxuart_platform_data uart_norts_pdata = {
-};
-
-
-static int mx21ads_fb_init(struct platform_device *pdev)
-{
- u16 tmp;
-
- tmp = __raw_readw(MX21ADS_IO_REG);
- tmp |= MX21ADS_IO_LCDON;
- __raw_writew(tmp, MX21ADS_IO_REG);
- return 0;
-}
-
-static void mx21ads_fb_exit(struct platform_device *pdev)
-{
- u16 tmp;
-
- tmp = __raw_readw(MX21ADS_IO_REG);
- tmp &= ~MX21ADS_IO_LCDON;
- __raw_writew(tmp, MX21ADS_IO_REG);
-}
-
-/*
- * Connected is a portrait Sharp-QVGA display
- * of type: LQ035Q7DB02
- */
-static struct imx_fb_videomode mx21ads_modes[] = {
- {
- .mode = {
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 188679, /* in ps (5.3MHz) */
- .hsync_len = 2,
- .left_margin = 6,
- .right_margin = 16,
- .vsync_len = 1,
- .upper_margin = 8,
- .lower_margin = 10,
- },
- .pcr = 0xfb108bc7,
- .bpp = 16,
- },
-};
-
-static struct imx_fb_platform_data mx21ads_fb_data = {
- .mode = mx21ads_modes,
- .num_modes = ARRAY_SIZE(mx21ads_modes),
-
- .pwmr = 0x00a903ff,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020008,
-
- .init = mx21ads_fb_init,
- .exit = mx21ads_fb_exit,
-};
-
-static int mx21ads_sdhc_get_ro(struct device *dev)
-{
- return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
-}
-
-static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = request_irq(IRQ_GPIOD(25), detect_irq,
- IRQF_TRIGGER_FALLING, "mmc-detect", data);
- if (ret)
- goto out;
- return 0;
-out:
- return ret;
-}
-
-static void mx21ads_sdhc_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_GPIOD(25), data);
-}
-
-static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
- .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
- .get_ro = mx21ads_sdhc_get_ro,
- .init = mx21ads_sdhc_init,
- .exit = mx21ads_sdhc_exit,
-};
-
-static struct mxc_nand_platform_data mx21ads_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct map_desc mx21ads_io_desc[] __initdata = {
- /*
- * Memory-mapped I/O on MX21ADS Base board:
- * - CS8900A Ethernet controller
- * - ST16C2552CJ UART
- * - CPU and Base board version
- * - Base board I/O register
- */
- {
- .virtual = MX21ADS_MMIO_BASE_ADDR,
- .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
- .length = MX21ADS_MMIO_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-static void __init mx21ads_map_io(void)
-{
- mx21_map_io();
- iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
-}
-
-static struct platform_device *platform_devices[] __initdata = {
- &mx21ads_nor_mtd_device,
-};
-
-static void __init mx21ads_board_init(void)
-{
- mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
- "mx21ads");
-
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
- mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
- mxc_register_device(&mxc_uart_device3, &uart_pdata);
- mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
- mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
- mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init mx21ads_timer_init(void)
-{
- mx21_clocks_init(32768, 26000000);
-}
-
-static struct sys_timer mx21ads_timer = {
- .init = mx21ads_timer_init,
-};
-
-MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
- /* maintainer: Freescale Semiconductor, Inc. */
- .phys_io = MX21_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX21_PHYS_OFFSET + 0x100,
- .map_io = mx21ads_map_io,
- .init_irq = mx21_init_irq,
- .init_machine = mx21ads_board_init,
- .timer = &mx21ads_timer,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-/*
- * This machine is known as:
- * - i.MX27 3-Stack Development System
- * - i.MX27 Platform Development Kit (i.MX27 PDK)
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx27.h>
-
-#include "devices.h"
-
-static unsigned int mx27pdk_pins[] = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
-};
-
-static struct imxuart_platform_data uart_pdata = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mxc_fec_device,
-};
-
-static void __init mx27pdk_init(void)
-{
- mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
- "mx27pdk");
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init mx27pdk_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-static struct sys_timer mx27pdk_timer = {
- .init = mx27pdk_timer_init,
-};
-
-MACHINE_START(MX27_3DS, "Freescale MX27PDK")
- /* maintainer: Freescale Semiconductor, Inc. */
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = mx27pdk_init,
- .timer = &mx27pdk_timer,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <mach/gpio.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
-#include <mach/i2c.h>
-#include <mach/imxfb.h>
-#include <mach/mmc.h>
-
-#include "devices.h"
-
-/*
- * Base address of PBC controller, CS4
- */
-#define PBC_BASE_ADDRESS 0xf4300000
-#define PBC_REG_ADDR(offset) (void __force __iomem *) \
- (PBC_BASE_ADDRESS + (offset))
-
-/* When the PBC address connection is fixed in h/w, defined as 1 */
-#define PBC_ADDR_SH 0
-
-/* Offsets for the PBC Controller register */
-/*
- * PBC Board version register offset
- */
-#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 set address.
- */
-#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 clear address.
- */
-#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
-
-/* PBC Board Control Register 1 bit definitions */
-#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
-
-/* to determine the correct external crystal reference */
-#define CKIH_27MHZ_BIT_SET (1 << 3)
-
-static unsigned int mx27ads_pins[] = {
- /* UART0 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* UART1 */
- PE3_PF_UART2_CTS,
- PE4_PF_UART2_RTS,
- PE6_PF_UART2_TXD,
- PE7_PF_UART2_RXD,
- /* UART2 */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
- PE10_PF_UART3_CTS,
- PE11_PF_UART3_RTS,
- /* UART3 */
- PB26_AF_UART4_RTS,
- PB28_AF_UART4_TXD,
- PB29_AF_UART4_CTS,
- PB31_AF_UART4_RXD,
- /* UART4 */
- PB18_AF_UART5_TXD,
- PB19_AF_UART5_RXD,
- PB20_AF_UART5_CTS,
- PB21_AF_UART5_RTS,
- /* UART5 */
- PB10_AF_UART6_TXD,
- PB12_AF_UART6_CTS,
- PB11_AF_UART6_RXD,
- PB13_AF_UART6_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* I2C2 */
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* FB */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA24_PF_REV,
- PA25_PF_CLS,
- PA26_PF_PS,
- PA27_PF_SPL_SPR,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
- /* OWIRE */
- PE16_AF_OWIRE,
- /* SDHC1*/
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
- /* SDHC2*/
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
-};
-
-static struct mxc_nand_platform_data mx27ads_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-/* ADS's NOR flash */
-static struct physmap_flash_data mx27ads_flash_data = {
- .width = 2,
-};
-
-static struct resource mx27ads_flash_resource = {
- .start = 0xc0000000,
- .end = 0xc0000000 + 0x02000000 - 1,
- .flags = IORESOURCE_MEM,
-
-};
-
-static struct platform_device mx27ads_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx27ads_flash_data,
- },
- .num_resources = 1,
- .resource = &mx27ads_flash_resource,
-};
-
-static struct imxi2c_platform_data mx27ads_i2c_data = {
- .bitrate = 100000,
-};
-
-static struct i2c_board_info mx27ads_i2c_devices[] = {
-};
-
-void lcd_power(int on)
-{
- if (on)
- __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
- else
- __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
-}
-
-static struct imx_fb_videomode mx27ads_modes[] = {
- {
- .mode = {
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 188679, /* in ps (5.3MHz) */
- .hsync_len = 1,
- .left_margin = 9,
- .right_margin = 16,
- .vsync_len = 1,
- .upper_margin = 7,
- .lower_margin = 9,
- },
- .bpp = 16,
- .pcr = 0xFB008BC0,
- },
-};
-
-static struct imx_fb_platform_data mx27ads_fb_data = {
- .mode = mx27ads_modes,
- .num_modes = ARRAY_SIZE(mx27ads_modes),
-
- /*
- * - HSYNC active high
- * - VSYNC active high
- * - clk notenabled while idle
- * - clock inverted
- * - data not inverted
- * - data enable low active
- * - enable sharp mode
- */
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020010,
-
- .lcd_power = lcd_power,
-};
-
-static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
- "sdhc1-card-detect", data);
-}
-
-static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
- "sdhc2-card-detect", data);
-}
-
-static void mx27ads_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_GPIOE(21), data);
-}
-
-static void mx27ads_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_GPIOB(7), data);
-}
-
-static struct imxmmc_platform_data sdhc1_pdata = {
- .init = mx27ads_sdhc1_init,
- .exit = mx27ads_sdhc1_exit,
-};
-
-static struct imxmmc_platform_data sdhc2_pdata = {
- .init = mx27ads_sdhc2_init,
- .exit = mx27ads_sdhc2_exit,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mx27ads_nor_mtd_device,
- &mxc_fec_device,
- &mxc_w1_master_device,
-};
-
-static struct imxuart_platform_data uart_pdata[] = {
- {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- },
-};
-
-static void __init mx27ads_board_init(void)
-{
- mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
- "mx27ads");
-
- mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
- mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
- mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
- mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
- mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
- mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
- mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
-
- /* only the i2c master 1 is used on this CPU card */
- i2c_register_board_info(1, mx27ads_i2c_devices,
- ARRAY_SIZE(mx27ads_i2c_devices));
- mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
- mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
- mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
- mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init mx27ads_timer_init(void)
-{
- unsigned long fref = 26000000;
-
- if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
- fref = 27000000;
-
- mx27_clocks_init(fref);
-}
-
-static struct sys_timer mx27ads_timer = {
- .init = mx27ads_timer_init,
-};
-
-static struct map_desc mx27ads_io_desc[] __initdata = {
- {
- .virtual = PBC_BASE_ADDRESS,
- .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
- .length = SZ_1M,
- .type = MT_DEVICE,
- },
-};
-
-static void __init mx27ads_map_io(void)
-{
- mx27_map_io();
- iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
-}
-
-MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
- /* maintainer: Freescale Semiconductor, Inc. */
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27ads_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = mx27ads_board_init,
- .timer = &mx27ads_timer,
-MACHINE_END
+++ /dev/null
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <linux/gpio.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
-#include <mach/i2c.h>
-#include <linux/i2c/pca953x.h>
-#include <mach/imxfb.h>
-#include <mach/mmc.h>
-
-#include "devices.h"
-
-static unsigned int mxt_td60_pins[] __initdata = {
- /* UART0 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* UART1 */
- PE3_PF_UART2_CTS,
- PE4_PF_UART2_RTS,
- PE6_PF_UART2_TXD,
- PE7_PF_UART2_RXD,
- /* UART2 */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
- PE10_PF_UART3_CTS,
- PE11_PF_UART3_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* I2C1 */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
- /* I2C2 */
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* FB */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA25_PF_CLS,
- PA27_PF_SPL_SPR,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
- /* OWIRE */
- PE16_AF_OWIRE,
- /* SDHC1*/
- PE18_PF_SD1_D0,
- PE19_PF_SD1_D1,
- PE20_PF_SD1_D2,
- PE21_PF_SD1_D3,
- PE22_PF_SD1_CMD,
- PE23_PF_SD1_CLK,
- PF8_AF_ATA_IORDY,
- /* SDHC2*/
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
-};
-
-static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct imxi2c_platform_data mxt_td60_i2c_data = {
- .bitrate = 100000,
-};
-
-/* PCA9557 */
-static int mxt_td60_pca9557_setup(struct i2c_client *client,
- unsigned gpio_base, unsigned ngpio,
- void *context)
-{
- static int mxt_td60_gpio_value[] = {
- -1, -1, -1, -1, -1, -1, -1, 1
- };
- int n;
-
- for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) {
- gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp");
- if (mxt_td60_gpio_value[n] < 0)
- gpio_direction_input(gpio_base + n);
- else
- gpio_direction_output(gpio_base + n,
- mxt_td60_gpio_value[n]);
- gpio_export(gpio_base + n, 0);
- }
-
- return 0;
-}
-
-static struct pca953x_platform_data mxt_td60_pca9557_pdata = {
- .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */
- .invert = 0, /* Do not invert */
- .setup = mxt_td60_pca9557_setup,
-};
-
-static struct i2c_board_info mxt_td60_i2c_devices[] = {
- {
- I2C_BOARD_INFO("pca9557", 0x18),
- .platform_data = &mxt_td60_pca9557_pdata,
- },
-};
-
-static struct imxi2c_platform_data mxt_td60_i2c2_data = {
- .bitrate = 100000,
-};
-
-static struct i2c_board_info mxt_td60_i2c2_devices[] = {
-};
-
-static struct imx_fb_videomode mxt_td60_modes[] = {
- {
- .mode = {
- .name = "Chimei LW700AT9003",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = 30303,
- .hsync_len = 64,
- .left_margin = 0x67,
- .right_margin = 0x68,
- .vsync_len = 16,
- .upper_margin = 0x0f,
- .lower_margin = 0x0f,
- },
- .bpp = 16,
- .pcr = 0xFA208B83,
- },
-};
-
-static struct imx_fb_platform_data mxt_td60_fb_data = {
- .mode = mxt_td60_modes,
- .num_modes = ARRAY_SIZE(mxt_td60_modes),
-
- /*
- * - HSYNC active high
- * - VSYNC active high
- * - clk notenabled while idle
- * - clock inverted
- * - data not inverted
- * - data enable low active
- * - enable sharp mode
- */
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020010,
-};
-
-static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
- "sdhc1-card-detect", data);
-}
-
-static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_GPIOF(8), data);
-}
-
-static struct imxmmc_platform_data sdhc1_pdata = {
- .init = mxt_td60_sdhc1_init,
- .exit = mxt_td60_sdhc1_exit,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mxc_fec_device,
-};
-
-static struct imxuart_platform_data uart_pdata[] = {
- {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- },
-};
-
-static void __init mxt_td60_board_init(void)
-{
- mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
- "MXT_TD60");
-
- mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
- mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
- mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
- mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
-
- i2c_register_board_info(0, mxt_td60_i2c_devices,
- ARRAY_SIZE(mxt_td60_i2c_devices));
-
- i2c_register_board_info(1, mxt_td60_i2c2_devices,
- ARRAY_SIZE(mxt_td60_i2c2_devices));
-
- mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
- mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
- mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
- mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init mxt_td60_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-static struct sys_timer mxt_td60_timer = {
- .init = mxt_td60_timer_init,
-};
-
-MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
- /* maintainer: Maxtrack Industrial */
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = mxt_td60_board_init,
- .timer = &mxt_td60_timer,
-MACHINE_END
-
+++ /dev/null
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-#include <linux/dma-mapping.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/eeprom.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx27.h>
-#include <mach/i2c.h>
-#include <asm/mach/time.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
-#include <mach/imx-uart.h>
-#include <mach/audmux.h>
-#include <mach/ssi.h>
-#include <mach/mxc_nand.h>
-#include <mach/irqs.h>
-#include <mach/mmc.h>
-#include <mach/mxc_ehci.h>
-#include <mach/ulpi.h>
-
-#include "devices.h"
-
-#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
-#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
-
-static int pca100_pins[] = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* SDHC */
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* SSI1 */
- PC20_PF_SSI1_FS,
- PC21_PF_SSI1_RXD,
- PC22_PF_SSI1_TXD,
- PC23_PF_SSI1_CLK,
- /* onboard I2C */
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* external I2C */
- PD17_PF_I2C_DATA,
- PD18_PF_I2C_CLK,
- /* SPI1 */
- PD25_PF_CSPI1_RDY,
- PD29_PF_CSPI1_SCLK,
- PD30_PF_CSPI1_MISO,
- PD31_PF_CSPI1_MOSI,
- /* OTG */
- OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PC7_PF_USBOTG_DATA5,
- PC8_PF_USBOTG_DATA6,
- PC9_PF_USBOTG_DATA0,
- PC10_PF_USBOTG_DATA2,
- PC11_PF_USBOTG_DATA1,
- PC12_PF_USBOTG_DATA4,
- PC13_PF_USBOTG_DATA3,
- PE0_PF_USBOTG_NXT,
- PE1_PF_USBOTG_STP,
- PE2_PF_USBOTG_DIR,
- PE24_PF_USBOTG_CLK,
- PE25_PF_USBOTG_DATA7,
- /* USBH2 */
- USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
-};
-
-static struct imxuart_platform_data uart_pdata = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct mxc_nand_platform_data pca100_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &mxc_w1_master_device,
- &mxc_fec_device,
- &mxc_wdt,
-};
-
-static struct imxi2c_platform_data pca100_i2c_1_data = {
- .bitrate = 100000,
-};
-
-static struct at24_platform_data board_eeprom = {
- .byte_len = 4096,
- .page_size = 32,
- .flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info pca100_i2c_devices[] = {
- {
- I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
- .platform_data = &board_eeprom,
- }, {
- I2C_BOARD_INFO("rtc-pcf8563", 0x51),
- .type = "pcf8563"
- }, {
- I2C_BOARD_INFO("lm75", 0x4a),
- .type = "lm75"
- }
-};
-
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-static struct spi_eeprom at25320 = {
- .name = "at25320an",
- .byte_len = 4096,
- .page_size = 32,
- .flags = EE_ADDR2,
-};
-
-static struct spi_board_info pca100_spi_board_info[] __initdata = {
- {
- .modalias = "at25",
- .max_speed_hz = 30000,
- .bus_num = 0,
- .chip_select = 1,
- .platform_data = &at25320,
- },
-};
-
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
-
-static struct spi_imx_master pca100_spi_0_data = {
- .chipselect = pca100_spi_cs,
- .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
-};
-#endif
-
-static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
-{
- mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
- gpio_set_value(GPIO_PORTC + 20, 1);
- udelay(2);
- gpio_set_value(GPIO_PORTC + 20, 0);
- mxc_gpio_mode(PC20_PF_SSI1_FS);
- msleep(2);
-}
-
-static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
-{
- mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
- gpio_set_value(GPIO_PORTC + 20, 0);
- mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
- gpio_set_value(GPIO_PORTC + 22, 0);
- mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
- gpio_set_value(GPIO_PORTC + 28, 0);
- udelay(10);
- gpio_set_value(GPIO_PORTC + 28, 1);
- mxc_gpio_mode(PC20_PF_SSI1_FS);
- mxc_gpio_mode(PC22_PF_SSI1_TXD);
- msleep(2);
-}
-
-static struct imx_ssi_platform_data pca100_ssi_pdata = {
- .ac97_reset = pca100_ac97_cold_reset,
- .ac97_warm_reset = pca100_ac97_warm_reset,
- .flags = IMX_SSI_USE_AC97,
-};
-
-static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = request_irq(IRQ_GPIOC(29), detect_irq,
- IRQF_DISABLED | IRQF_TRIGGER_FALLING,
- "imx-mmc-detect", data);
- if (ret)
- printk(KERN_ERR
- "pca100: Failed to reuest irq for sd/mmc detection\n");
-
- return ret;
-}
-
-static void pca100_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_GPIOC(29), data);
-}
-
-static struct imxmmc_platform_data sdhc_pdata = {
- .init = pca100_sdhc2_init,
- .exit = pca100_sdhc2_exit,
-};
-
-static int otg_phy_init(struct platform_device *pdev)
-{
- gpio_set_value(OTG_PHY_CS_GPIO, 0);
- return 0;
-}
-
-static struct mxc_usbh_platform_data otg_pdata = {
- .init = otg_phy_init,
- .portsc = MXC_EHCI_MODE_ULPI,
- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
-};
-
-static int usbh2_phy_init(struct platform_device *pdev)
-{
- gpio_set_value(USBH2_PHY_CS_GPIO, 0);
- return 0;
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata = {
- .init = usbh2_phy_init,
- .portsc = MXC_EHCI_MODE_ULPI,
- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
-};
-
-static struct fsl_usb2_platform_data otg_device_pdata = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static int otg_mode_host;
-
-static int __init pca100_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = 1;
- else if (!strcmp(options, "device"))
- otg_mode_host = 0;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 0;
-}
-__setup("otg_mode=", pca100_otg_mode);
-
-static void __init pca100_init(void)
-{
- int ret;
-
- /* SSI unit */
- mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
- MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
- MXC_AUDMUX_V1_PCR_TFCSEL(3) |
- MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
- MXC_AUDMUX_V1_PCR_RXDSEL(3));
- mxc_audmux_v1_configure_port(3,
- MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
- MXC_AUDMUX_V1_PCR_TFCSEL(0) |
- MXC_AUDMUX_V1_PCR_TFSDIR |
- MXC_AUDMUX_V1_PCR_RXDSEL(0));
-
- ret = mxc_gpio_setup_multiple_pins(pca100_pins,
- ARRAY_SIZE(pca100_pins), "PCA100");
- if (ret)
- printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
-
- mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
-
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
- mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
- mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
-
- mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
-
- /* only the i2c master 1 is used on this CPU card */
- i2c_register_board_info(1, pca100_i2c_devices,
- ARRAY_SIZE(pca100_i2c_devices));
-
- mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
-
- mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
- mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
- /* GPIO0_IRQ */
- mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
- /* GPIO1_IRQ */
- mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
- /* GPIO2_IRQ */
- mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
-
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
- spi_register_board_info(pca100_spi_board_info,
- ARRAY_SIZE(pca100_spi_board_info));
- mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
-#endif
-
- gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
- gpio_direction_output(OTG_PHY_CS_GPIO, 1);
- gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
- gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
-
-#if defined(CONFIG_USB_ULPI)
- if (otg_mode_host) {
- otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
-
- mxc_register_device(&mxc_otg_host, &otg_pdata);
- }
-
- usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
- USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
-
- mxc_register_device(&mxc_usbh2, &usbh2_pdata);
-#endif
- if (!otg_mode_host) {
- gpio_set_value(OTG_PHY_CS_GPIO, 0);
- mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
- }
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
-
-static void __init pca100_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-static struct sys_timer pca100_timer = {
- .init = pca100_timer_init,
-};
-
-MACHINE_START(PCA100, "phyCARD-i.MX27")
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = pca100_init,
- .timer = &pca100_timer,
-MACHINE_END
-
+++ /dev/null
-/*
- * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-#include <linux/io.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/board-pcm038.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
-#include <mach/mxc_ehci.h>
-#include <mach/ulpi.h>
-
-#include "devices.h"
-
-static int pcm038_pins[] = {
- /* UART1 */
- PE12_PF_UART1_TXD,
- PE13_PF_UART1_RXD,
- PE14_PF_UART1_CTS,
- PE15_PF_UART1_RTS,
- /* UART2 */
- PE3_PF_UART2_CTS,
- PE4_PF_UART2_RTS,
- PE6_PF_UART2_TXD,
- PE7_PF_UART2_RXD,
- /* UART3 */
- PE8_PF_UART3_TXD,
- PE9_PF_UART3_RXD,
- PE10_PF_UART3_CTS,
- PE11_PF_UART3_RTS,
- /* FEC */
- PD0_AIN_FEC_TXD0,
- PD1_AIN_FEC_TXD1,
- PD2_AIN_FEC_TXD2,
- PD3_AIN_FEC_TXD3,
- PD4_AOUT_FEC_RX_ER,
- PD5_AOUT_FEC_RXD1,
- PD6_AOUT_FEC_RXD2,
- PD7_AOUT_FEC_RXD3,
- PD8_AF_FEC_MDIO,
- PD9_AIN_FEC_MDC,
- PD10_AOUT_FEC_CRS,
- PD11_AOUT_FEC_TX_CLK,
- PD12_AOUT_FEC_RXD0,
- PD13_AOUT_FEC_RX_DV,
- PD14_AOUT_FEC_RX_CLK,
- PD15_AOUT_FEC_COL,
- PD16_AIN_FEC_TX_ER,
- PF23_AIN_FEC_TX_EN,
- /* I2C2 */
- PC5_PF_I2C2_SDA,
- PC6_PF_I2C2_SCL,
- /* SPI1 */
- PD25_PF_CSPI1_RDY,
- PD29_PF_CSPI1_SCLK,
- PD30_PF_CSPI1_MISO,
- PD31_PF_CSPI1_MOSI,
- /* SSI1 */
- PC20_PF_SSI1_FS,
- PC21_PF_SSI1_RXD,
- PC22_PF_SSI1_TXD,
- PC23_PF_SSI1_CLK,
- /* SSI4 */
- PC16_PF_SSI4_FS,
- PC17_PF_SSI4_RXD,
- PC18_PF_SSI4_TXD,
- PC19_PF_SSI4_CLK,
- /* USB host */
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
-};
-
-/*
- * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
- * 16 bit width
- */
-
-static struct platdata_mtd_ram pcm038_sram_data = {
- .bankwidth = 2,
-};
-
-static struct resource pcm038_sram_resource = {
- .start = MX27_CS1_BASE_ADDR,
- .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm038_sram_mtd_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &pcm038_sram_data,
- },
- .num_resources = 1,
- .resource = &pcm038_sram_resource,
-};
-
-/*
- * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
- * 16 bit width
- */
-static struct physmap_flash_data pcm038_flash_data = {
- .width = 2,
-};
-
-static struct resource pcm038_flash_resource = {
- .start = 0xc0000000,
- .end = 0xc1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm038_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &pcm038_flash_data,
- },
- .num_resources = 1,
- .resource = &pcm038_flash_resource,
-};
-
-static struct imxuart_platform_data uart_pdata[] = {
- {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- }, {
- .flags = IMXUART_HAVE_RTSCTS,
- },
-};
-
-static struct mxc_nand_platform_data pcm038_nand_board_info = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &pcm038_nor_mtd_device,
- &mxc_w1_master_device,
- &mxc_fec_device,
- &pcm038_sram_mtd_device,
- &mxc_wdt,
-};
-
-/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
- * setup other stuffs to access the sram. */
-static void __init pcm038_init_sram(void)
-{
- mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
-}
-
-static struct imxi2c_platform_data pcm038_i2c_1_data = {
- .bitrate = 100000,
-};
-
-static struct at24_platform_data board_eeprom = {
- .byte_len = 4096,
- .page_size = 32,
- .flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info pcm038_i2c_devices[] = {
- {
- I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
- .platform_data = &board_eeprom,
- }, {
- I2C_BOARD_INFO("pcf8563", 0x51),
- }, {
- I2C_BOARD_INFO("lm75", 0x4a),
- }
-};
-
-static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
-
-static struct spi_imx_master pcm038_spi_0_data = {
- .chipselect = pcm038_spi_cs,
- .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
-};
-
-static struct regulator_consumer_supply sdhc1_consumers[] = {
- {
- .dev = &mxc_sdhc_device1.dev,
- .supply = "sdhc_vcc",
- },
-};
-
-static struct regulator_init_data sdhc1_data = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3400000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .always_on = 0,
- .boot_on = 0,
- },
- .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers),
- .consumer_supplies = sdhc1_consumers,
-};
-
-static struct regulator_consumer_supply cam_consumers[] = {
- {
- .dev = NULL,
- .supply = "imx_cam_vcc",
- },
-};
-
-static struct regulator_init_data cam_data = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3400000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .always_on = 0,
- .boot_on = 0,
- },
- .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
- .consumer_supplies = cam_consumers,
-};
-
-struct mc13783_regulator_init_data pcm038_regulators[] = {
- {
- .id = MC13783_REGU_VCAM,
- .init_data = &cam_data,
- }, {
- .id = MC13783_REGU_VMMC1,
- .init_data = &sdhc1_data,
- },
-};
-
-static struct mc13783_platform_data pcm038_pmic = {
- .regulators = pcm038_regulators,
- .num_regulators = ARRAY_SIZE(pcm038_regulators),
- .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR |
- MC13783_USE_TOUCHSCREEN,
-};
-
-static struct spi_board_info pcm038_spi_board_info[] __initdata = {
- {
- .modalias = "mc13783",
- .irq = IRQ_GPIOB(23),
- .max_speed_hz = 300000,
- .bus_num = 0,
- .chip_select = 0,
- .platform_data = &pcm038_pmic,
- .mode = SPI_CS_HIGH,
- }
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata = {
- .portsc = MXC_EHCI_MODE_ULPI,
- .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
-};
-
-static void __init pcm038_init(void)
-{
- mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
- "PCM038");
-
- pcm038_init_sram();
-
- mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
- mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
- mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-
- mxc_gpio_mode(PE16_AF_OWIRE);
- mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
-
- /* only the i2c master 1 is used on this CPU card */
- i2c_register_board_info(1, pcm038_i2c_devices,
- ARRAY_SIZE(pcm038_i2c_devices));
-
- mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
-
- /* PE18 for user-LED D40 */
- mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
-
- mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-
- /* MC13783 IRQ */
- mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
-
- mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
- spi_register_board_info(pcm038_spi_board_info,
- ARRAY_SIZE(pcm038_spi_board_info));
-
- mxc_register_device(&mxc_usbh2, &usbh2_pdata);
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-#ifdef CONFIG_MACH_PCM970_BASEBOARD
- pcm970_baseboard_init();
-#endif
-}
-
-static void __init pcm038_timer_init(void)
-{
- mx27_clocks_init(26000000);
-}
-
-static struct sys_timer pcm038_timer = {
- .init = pcm038_timer_init,
-};
-
-MACHINE_START(PCM038, "phyCORE-i.MX27")
- .phys_io = MX27_AIPI_BASE_ADDR,
- .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
- .boot_params = MX27_PHYS_OFFSET + 0x100,
- .map_io = mx27_map_io,
- .init_irq = mx27_init_irq,
- .init_machine = pcm038_init,
- .timer = &pcm038_timer,
-MACHINE_END
+++ /dev/null
-/*
- * arch/arm/mach-mx2/mm-imx21.c
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-/* MX21 memory map definition */
-static struct map_desc imx21_io_desc[] __initdata = {
- /*
- * this fixed mapping covers:
- * - AIPI1
- * - AIPI2
- * - AITC
- * - ROM Patch
- * - and some reserved space
- */
- {
- .virtual = MX21_AIPI_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
- .length = MX21_AIPI_SIZE,
- .type = MT_DEVICE
- },
- /*
- * this fixed mapping covers:
- * - CSI
- * - ATA
- */
- {
- .virtual = MX21_SAHB1_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
- .length = MX21_SAHB1_SIZE,
- .type = MT_DEVICE
- },
- /*
- * this fixed mapping covers:
- * - EMI
- */
- {
- .virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
- .length = MX21_X_MEMC_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/*
- * Initialize the memory map. It is called during the
- * system startup to create static physical to virtual
- * memory map for the IO modules.
- */
-void __init mx21_map_io(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX21);
- mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
-
- iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
-}
-
-void __init mx21_init_irq(void)
-{
- mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
-}
+++ /dev/null
-/*
- * arch/arm/mach-mx2/mm-imx27.c
- *
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-/* MX27 memory map definition */
-static struct map_desc imx27_io_desc[] __initdata = {
- /*
- * this fixed mapping covers:
- * - AIPI1
- * - AIPI2
- * - AITC
- * - ROM Patch
- * - and some reserved space
- */
- {
- .virtual = MX27_AIPI_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
- .length = MX27_AIPI_SIZE,
- .type = MT_DEVICE
- },
- /*
- * this fixed mapping covers:
- * - CSI
- * - ATA
- */
- {
- .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
- .length = MX27_SAHB1_SIZE,
- .type = MT_DEVICE
- },
- /*
- * this fixed mapping covers:
- * - EMI
- */
- {
- .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
- .length = MX27_X_MEMC_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/*
- * Initialize the memory map. It is called during the
- * system startup to create static physical to virtual
- * memory map for the IO modules.
- */
-void __init mx27_map_io(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX27);
- mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
-
- iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
-}
-
-void __init mx27_init_irq(void)
-{
- mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
-}
+++ /dev/null
-/*
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/can/platform/sja1000.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx27.h>
-#include <mach/imxfb.h>
-#include <mach/hardware.h>
-#include <mach/mmc.h>
-
-#include "devices.h"
-
-static int pcm970_pins[] = {
- /* SDHC */
- PB4_PF_SD2_D0,
- PB5_PF_SD2_D1,
- PB6_PF_SD2_D2,
- PB7_PF_SD2_D3,
- PB8_PF_SD2_CMD,
- PB9_PF_SD2_CLK,
- /* display */
- PA5_PF_LSCLK,
- PA6_PF_LD0,
- PA7_PF_LD1,
- PA8_PF_LD2,
- PA9_PF_LD3,
- PA10_PF_LD4,
- PA11_PF_LD5,
- PA12_PF_LD6,
- PA13_PF_LD7,
- PA14_PF_LD8,
- PA15_PF_LD9,
- PA16_PF_LD10,
- PA17_PF_LD11,
- PA18_PF_LD12,
- PA19_PF_LD13,
- PA20_PF_LD14,
- PA21_PF_LD15,
- PA22_PF_LD16,
- PA23_PF_LD17,
- PA24_PF_REV,
- PA25_PF_CLS,
- PA26_PF_PS,
- PA27_PF_SPL_SPR,
- PA28_PF_HSYNC,
- PA29_PF_VSYNC,
- PA30_PF_CONTRAST,
- PA31_PF_OE_ACD,
- /*
- * it seems the data line misses a pullup, so we must enable
- * the internal pullup as a local workaround
- */
- PD17_PF_I2C_DATA | GPIO_PUEN,
- PD18_PF_I2C_CLK,
- /* Camera */
- PB10_PF_CSI_D0,
- PB11_PF_CSI_D1,
- PB12_PF_CSI_D2,
- PB13_PF_CSI_D3,
- PB14_PF_CSI_D4,
- PB15_PF_CSI_MCLK,
- PB16_PF_CSI_PIXCLK,
- PB17_PF_CSI_D5,
- PB18_PF_CSI_D6,
- PB19_PF_CSI_D7,
- PB20_PF_CSI_VSYNC,
- PB21_PF_CSI_HSYNC,
-};
-
-static int pcm970_sdhc2_get_ro(struct device *dev)
-{
- return gpio_get_value(GPIO_PORTC + 28);
-}
-
-static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
-{
- int ret;
-
- ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
- "imx-mmc-detect", data);
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
- if (ret) {
- free_irq(IRQ_GPIOC(29), data);
- return ret;
- }
-
- gpio_direction_input(GPIO_PORTC + 28);
-
- return 0;
-}
-
-static void pcm970_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(IRQ_GPIOC(29), data);
- gpio_free(GPIO_PORTC + 28);
-}
-
-static struct imxmmc_platform_data sdhc_pdata = {
- .get_ro = pcm970_sdhc2_get_ro,
- .init = pcm970_sdhc2_init,
- .exit = pcm970_sdhc2_exit,
-};
-
-static struct imx_fb_videomode pcm970_modes[] = {
- {
- .mode = {
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 188679, /* in ps (5.3MHz) */
- .hsync_len = 7,
- .left_margin = 5,
- .right_margin = 16,
- .vsync_len = 1,
- .upper_margin = 7,
- .lower_margin = 9,
- },
- /*
- * - HSYNC active high
- * - VSYNC active high
- * - clk notenabled while idle
- * - clock not inverted
- * - data not inverted
- * - data enable low active
- * - enable sharp mode
- */
- .pcr = 0xF00080C0,
- .bpp = 16,
- }, {
- .mode = {
- .name = "TX090",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 38255,
- .left_margin = 144,
- .right_margin = 0,
- .upper_margin = 7,
- .lower_margin = 40,
- .hsync_len = 96,
- .vsync_len = 1,
- },
- /*
- * - HSYNC active low (1 << 22)
- * - VSYNC active low (1 << 23)
- * - clk notenabled while idle
- * - clock not inverted
- * - data not inverted
- * - data enable low active
- * - enable sharp mode
- */
- .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
- .bpp = 32,
- },
-};
-
-static struct imx_fb_platform_data pcm038_fb_data = {
- .mode = pcm970_modes,
- .num_modes = ARRAY_SIZE(pcm970_modes),
-
- .pwmr = 0x00A903FF,
- .lscr1 = 0x00120300,
- .dmacr = 0x00020010,
-};
-
-static struct resource pcm970_sja1000_resources[] = {
- {
- .start = MX27_CS4_BASE_ADDR,
- .end = MX27_CS4_BASE_ADDR + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_GPIOE(19),
- .end = IRQ_GPIOE(19),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-struct sja1000_platform_data pcm970_sja1000_platform_data = {
- .osc_freq = 16000000,
- .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
- .cdr = CDR_CBP,
-};
-
-static struct platform_device pcm970_sja1000 = {
- .name = "sja1000_platform",
- .dev = {
- .platform_data = &pcm970_sja1000_platform_data,
- },
- .resource = pcm970_sja1000_resources,
- .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
-};
-
-/*
- * system init for baseboard usage. Will be called by pcm038 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init pcm970_baseboard_init(void)
-{
- mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
- "PCM970");
-
- mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
- mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
- mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
- platform_device_register(&pcm970_sja1000);
-}
+++ /dev/null
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include "devices.h"
-
-static struct resource uart0[] = {
- {
- .start = MX2x_UART1_BASE_ADDR,
- .end = MX2x_UART1_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX2x_INT_UART1,
- .end = MX2x_INT_UART1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device0 = {
- .name = "imx-uart",
- .id = 0,
- .resource = uart0,
- .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
- {
- .start = MX2x_UART2_BASE_ADDR,
- .end = MX2x_UART2_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX2x_INT_UART2,
- .end = MX2x_INT_UART2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device1 = {
- .name = "imx-uart",
- .id = 1,
- .resource = uart1,
- .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
- {
- .start = MX2x_UART3_BASE_ADDR,
- .end = MX2x_UART3_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX2x_INT_UART3,
- .end = MX2x_INT_UART3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device2 = {
- .name = "imx-uart",
- .id = 2,
- .resource = uart2,
- .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
- {
- .start = MX2x_UART4_BASE_ADDR,
- .end = MX2x_UART4_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX2x_INT_UART4,
- .end = MX2x_INT_UART4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device3 = {
- .name = "imx-uart",
- .id = 3,
- .resource = uart3,
- .num_resources = ARRAY_SIZE(uart3),
-};
-
-#ifdef CONFIG_MACH_MX27
-static struct resource uart4[] = {
- {
- .start = MX27_UART5_BASE_ADDR,
- .end = MX27_UART5_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX27_INT_UART5,
- .end = MX27_INT_UART5,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device4 = {
- .name = "imx-uart",
- .id = 4,
- .resource = uart4,
- .num_resources = ARRAY_SIZE(uart4),
-};
-
-static struct resource uart5[] = {
- {
- .start = MX27_UART6_BASE_ADDR,
- .end = MX27_UART6_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX27_INT_UART6,
- .end = MX27_INT_UART6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device5 = {
- .name = "imx-uart",
- .id = 5,
- .resource = uart5,
- .num_resources = ARRAY_SIZE(uart5),
-};
-#endif
endchoice
source "arch/arm/mach-mx1/Kconfig"
-source "arch/arm/mach-mx2/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-mx3/Kconfig"
source "arch/arm/mach-mx25/Kconfig"
source "arch/arm/mach-mxc91231/Kconfig"
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / commitdiff