iommu/arm-smmu: caps: add IOMMU_CAP_INTR_REMAP capability

MSIs are just seen as bog standard memory writes by the ARM SMMU, so
they can be translated (and isolated) in the same way.

This patch adds the IOMMU_CAP_INTR_REMAP capability to the ARM SMMU
driver and reworks our capabaility code so that we don't assume the
caps are organised as bits in a bitmask (since this isn't the intention).

Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 373b6e4d6e15ea0c26485a37e8fe4c67f3427f70..3ae50be49269d8daa77f0565ce59fd97cf7659ce 100644 (file)
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1606,13 +1606,17 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
                                   unsigned long cap)
 {
-       unsigned long caps = 0;
        struct arm_smmu_domain *smmu_domain = domain->priv;
+       u32 features = smmu_domain->root_cfg.smmu->features;
 
-       if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
-               caps |= IOMMU_CAP_CACHE_COHERENCY;
-
-       return !!(cap & caps);
+       switch (cap) {
+       case IOMMU_CAP_CACHE_COHERENCY:
+               return features & ARM_SMMU_FEAT_COHERENT_WALK;
+       case IOMMU_CAP_INTR_REMAP:
+               return 1; /* MSIs are just memory writes */
+       default:
+               return 0;
+       }
 }
 
 static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)