rt2x00:Add RT5392 chipset support
authorZero.Lin <Zero.Lin@mediatek.com>
Tue, 29 May 2012 08:11:09 +0000 (16:11 +0800)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 6 Jun 2012 19:19:00 +0000 (15:19 -0400)
Signed-off-by: Zero.Lin <Zero.Lin@mediatek.com>
Reviewed-by: Stanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/rt2x00/rt2800.h
drivers/net/wireless/rt2x00/rt2800lib.c

index 6403f49da41946284242e432843466a7f40a0e8d..1ca88cdc6eced82ec9d84e460c0398c4c3e4f50f 100644 (file)
@@ -72,6 +72,7 @@
 #define RF5370                         0x5370
 #define RF5372                         0x5372
 #define RF5390                         0x5390
+#define RF5392                         0x5392
 
 /*
  * Chipset revisions.
@@ -1945,6 +1946,11 @@ struct mac_iveiv_entry {
  */
 #define RFCSR49_TX                     FIELD8(0x3f)
 
+/*
+ * RFCSR 50:
+ */
+#define RFCSR50_TX                     FIELD8(0x3f)
+
 /*
  * RF registers
  */
index 11488e743f08be808681d91551f6abd8f29beb35..4d3747c3010b987134199dabf09d0815f269987e 100644 (file)
@@ -1958,7 +1958,22 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
                rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
        rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
 
+       if (rt2x00_rt(rt2x00dev, RT5392)) {
+               rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
+               if (info->default_power1 > RT5390_POWER_BOUND)
+                       rt2x00_set_field8(&rfcsr, RFCSR50_TX,
+                                         RT5390_POWER_BOUND);
+               else
+                       rt2x00_set_field8(&rfcsr, RFCSR50_TX,
+                                         info->default_power2);
+               rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
+       }
+
        rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
+       if (rt2x00_rt(rt2x00dev, RT5392)) {
+               rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
+               rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
+       }
        rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
        rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
        rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
@@ -2064,6 +2079,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
        case RF5370:
        case RF5372:
        case RF5390:
+       case RF5392:
                rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
                break;
        default:
@@ -2554,6 +2570,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
        case RF5370:
        case RF5372:
        case RF5390:
+       case RF5392:
                rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
                rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
                rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
@@ -4269,6 +4286,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
        case RF5370:
        case RF5372:
        case RF5390:
+       case RF5392:
                break;
        default:
                ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
@@ -4583,7 +4601,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
                   rt2x00_rf(rt2x00dev, RF5360) ||
                   rt2x00_rf(rt2x00dev, RF5370) ||
                   rt2x00_rf(rt2x00dev, RF5372) ||
-                  rt2x00_rf(rt2x00dev, RF5390)) {
+                  rt2x00_rf(rt2x00dev, RF5390) ||
+                  rt2x00_rf(rt2x00dev, RF5392)) {
                spec->num_channels = 14;
                spec->channels = rf_vals_3x;
        } else if (rt2x00_rf(rt2x00dev, RF3052)) {
@@ -4670,6 +4689,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
        case RF5370:
        case RF5372:
        case RF5390:
+       case RF5392:
                __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
                break;
        }