drm/i915: Apply a big hammer to 865 GEM object CPU cache flushing.

On the 865, but not the 855, the clflush we do appears to not actually make
it out to the hardware all the time.  An easy way to safely reproduce was
X -retro, which would show that some of the blits involved in drawing the
lovely root weave didn't make it out to the hardware.  Those blits are 32
bytes each, and 1-2 would be missing at various points around the screen.
Other experimentation (doing more clflush, doing more AGP chipset flush,
poking at some more device registers to maybe trigger more flushing) didn't
help.  krh came up with the wbinvd as a way to successfully get all those
blits to appear.

Signed-off-by: Eric Anholt <eric@anholt.net>

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4408daf8cef099d388611268be5cbd5605c1dc4..e2421869a40cf809f509c57e58a770a7c0e4043a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2423,6 +2423,16 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
        if (obj_priv->pages == NULL)
                return;
 
+       /* XXX: The 865 in particular appears to be weird in how it handles
+        * cache flushing.  We haven't figured it out, but the
+        * clflush+agp_chipset_flush doesn't appear to successfully get the
+        * data visible to the PGU, while wbinvd + agp_chipset_flush does.
+        */
+       if (IS_I865G(obj->dev)) {
+               wbinvd();
+               return;
+       }
+
        drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
 }