arm64: dts: rockchip: add rk3368 iommu nodes

Add IEP/ISP/VOP/HEVC/VPU iommu nodes

Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index e4f6be0c562b89b1256e6093e5a13ef1ec83209f..e0518b4bc6c2a018963787d0096077ab540b78e8 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -805,6 +805,55 @@
                status = "disabled";
        };
 
+       iep_mmu: iommu@ff900800 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff900800 0x0 0x100>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "iep_mmu";
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       isp_mmu: iommu@ff914000 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff914000 0x0 0x100>,
+                     <0x0 0xff915000 0x0 0x100>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "isp_mmu";
+               #iommu-cells = <0>;
+               rockchip,disable-mmu-reset;
+               status = "disabled";
+       };
+
+       vop_mmu: iommu@ff930300 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff930300 0x0 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vop_mmu";
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       hevc_mmu: iommu@ff9a0440 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff9a0440 0x0 0x40>,
+                     <0x0 0xff9a0480 0x0 0x40>;
+               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "hevc_mmu";
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
+       vpu_mmu: iommu@ff9a0800 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff9a0800 0x0 0x100>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vepu_mmu", "vdpu_mmu";
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
        gic: interrupt-controller@ffb71000 {
                compatible = "arm,gic-400";
                interrupt-controller;