soc: renesas: rcar-sysc: Improve SYSC interrupt config in legacy wrapper
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 28 Jun 2016 14:10:34 +0000 (16:10 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 29 Jun 2016 12:37:24 +0000 (14:37 +0200)
Align SYSC interrupt configuration in the legacy wrapper with the DT
version:
  - Mask SYSC interrupt sources before enabling them (doesn't matter
    much as they're disabled at the GIC level anyway),
  - Make sure not to clear reserved SYSCIMR bits that were set before.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
drivers/soc/renesas/rcar-sysc.c

index 22f0d646225c444ecf39ba4dd9a95e4bd0e3fd7a..65c8e1eb90c09bb352acea559e619d0e87cbf5a9 100644 (file)
@@ -402,12 +402,25 @@ early_initcall(rcar_sysc_pd_init);
 
 void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
 {
+       u32 syscimr;
+
        if (!rcar_sysc_pd_init())
                return;
 
        rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
 
-       /* enable all interrupt sources, but do not use interrupt handler */
+       /*
+        * Mask all interrupt sources to prevent the CPU from receiving them.
+        * Make sure not to clear reserved bits that were set before.
+        */
+       syscimr = ioread32(rcar_sysc_base + SYSCIMR);
+       syscimr |= syscier;
+       pr_debug("%s: syscimr = 0x%08x\n", __func__, syscimr);
+       iowrite32(syscimr, rcar_sysc_base + SYSCIMR);
+
+       /*
+        * SYSC needs all interrupt sources enabled to control power.
+        */
+       pr_debug("%s: syscier = 0x%08x\n", __func__, syscier);
        iowrite32(syscier, rcar_sysc_base + SYSCIER);
-       iowrite32(0, rcar_sysc_base + SYSCIMR);
 }