clk: tegra: Make gr2d and gr3d clocks children of pll_c

By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.

gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b92d48be4cc93dab2deb7ad561912f112fecd860..f87bd4a8c3248f57319d88d2dad4d2b2812ba6b8 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1247,6 +1247,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
        {host1x, pll_c, 150000000, 0},
        {disp1, pll_p, 600000000, 0},
        {disp2, pll_p, 600000000, 0},
+       {gr2d, pll_c, 300000000, 0},
+       {gr3d, pll_c, 300000000, 0},
        {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
 };
 

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ba6f51bc9f3b8bc229bf0900ff380002fbb51e14..b8b241de3f4c49f26c0aa166725c384b325ad7c1 100644 (file)
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1911,6 +1911,8 @@ static __initdata struct tegra_clk_init_table init_table[] = {
        {disp1, pll_p, 600000000, 0},
        {disp2, pll_p, 600000000, 0},
        {twd, clk_max, 0, 1},
+       {gr2d, pll_c, 300000000, 0},
+       {gr3d, pll_c, 300000000, 0},
        {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
 };