clk: exynos5420: fix cpll clock register offsets
authorChander Kashyap <chander.kashyap@linaro.org>
Thu, 26 Sep 2013 09:06:35 +0000 (14:36 +0530)
committerMike Turquette <mturquette@linaro.org>
Wed, 4 Dec 2013 18:46:45 +0000 (10:46 -0800)
Fixes cpll control and lock register offset values for Exynos5420 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/samsung/clk-exynos5420.c

index 48c4a9350b91172d6222ed74b95862e223f802ad..87ea79633862f4bfeb164fae5ee8803d8c8b0f1d 100644 (file)
@@ -737,8 +737,8 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
        [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
                APLL_CON0, NULL),
-       [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
-               MPLL_CON0, NULL),
+       [cpll] = PLL(pll_2550, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
+               CPLL_CON0, NULL),
        [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK,
                DPLL_CON0, NULL),
        [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,