[RAMEN9610-10029][COMMON] media: mfc: fix interlace processing when NAL_Q mode
authorSunyoung Kang <sy0816.kang@samsung.com>
Thu, 13 Sep 2018 07:17:20 +0000 (16:17 +0900)
committerhskang <hs1218.kang@samsung.com>
Fri, 28 Dec 2018 09:53:54 +0000 (18:53 +0900)
The H264/VC1/MPEG2/MPEG4 codec can have interlace type.
But the only MPEG4 can continue to use NAL_Q mode
because it doesn't handle field unit.
The other codecs should stop NAL_Q mode and use NAL_START.

Change-Id: Ied5972b8f567d91290ca937efd25ae14f9ece19e
Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
drivers/media/platform/exynos/mfc/mfc_nal_q.c
drivers/media/platform/exynos/mfc/mfc_regs.h

index 0bc18f782f4e4fb1cb59856910d9c1d01d46ede5..e3889948e95654821621ad589c9ce1d5dc6f8ec1 100644 (file)
@@ -1622,9 +1622,9 @@ void __mfc_nal_q_handle_frame(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr)
        need_scratch_change = (pOutStr->DisplayStatus
                                 >> MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_SHIFT)
                                & MFC_REG_DISP_STATUS_NEED_SCRATCH_CHANGE_MASK;
-       is_interlaced = (pOutStr->DisplayStatus
-                               >> MFC_REG_DISP_STATUS_INTERLACE_SHIFT)
-                               & MFC_REG_DISP_STATUS_INTERLACE_MASK;
+       is_interlaced = (pOutStr->DecodedStatus
+                               >> MFC_REG_DEC_STATUS_INTERLACE_SHIFT)
+                               & MFC_REG_DEC_STATUS_INTERLACE_MASK;
        sei_avail_status = pOutStr->SeiAvail;
        err = pOutStr->ErrorCode;
 
@@ -1671,7 +1671,12 @@ void __mfc_nal_q_handle_frame(struct mfc_ctx *ctx, DecoderOutputStr *pOutStr)
                mfc_change_state(ctx, MFCINST_ERROR);
                goto leave_handle_frame;
        }
-       if (is_interlaced) {
+       /*
+        * H264/VC1/MPEG2/MPEG4 can have interlace type
+        * Only MPEG4 can continue to use NALQ
+        * because MPEG4 doesn't handle field unit.
+        */
+       if (is_interlaced && !IS_MPEG4_DEC(ctx)) {
                mfc_debug(2, "[NALQ][INTERLACE] Progressive -> Interlaced\n");
                dec->is_interlaced = is_interlaced;
                dev->nal_q_handle->nal_q_exception = 1;
index 17e89acba767842f57f7adadacabfca6572d33fa..cf7537695115e10168c70475f68418c41168c9df 100644 (file)
 #define MFC_REG_DEC_STATUS_DECODING_EMPTY              3
 #define MFC_REG_DEC_STATUS_NUM_OF_TILE_MASK            0xF
 #define MFC_REG_DEC_STATUS_NUM_OF_TILE_SHIFT           15
+#define MFC_REG_DEC_STATUS_INTERLACE_MASK              0x1
+#define MFC_REG_DEC_STATUS_INTERLACE_SHIFT             3
 
 
 /* 0xF654: MFC_REG_D_DECODED_FRAME_TYPE */