drm/amd/powerplay: change parameter type pointer from int32_t to void in read sensor

As well as fix print format for uint32_t type.

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index fd45212c4b98a64a3d13be09ad9e2b1a5191ea6d..fc4d61cf34c10a0ae8b0b6e2e2edaabd2a32bc59 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1532,7 +1532,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
 
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
 {
-       int32_t value;
+       uint32_t value;
 
        /* sanity check PP is enabled */
        if (!(adev->powerplay.pp_funcs &&
@@ -1541,46 +1541,46 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
 
        /* GPU Clocks */
        seq_printf(m, "GFX Clocks and Power:\n");
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value))
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value))
                seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value))
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value))
                seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value))
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value))
                seq_printf(m, "\t%u mV (VDDGFX)\n", value);
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value))
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value))
                seq_printf(m, "\t%u mV (VDDNB)\n", value);
        seq_printf(m, "\n");
 
        /* GPU Temp */
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value))
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value))
                seq_printf(m, "GPU Temperature: %u C\n", value/1000);
 
        /* GPU Load */
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value))
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value))
                seq_printf(m, "GPU Load: %u %%\n", value);
        seq_printf(m, "\n");
 
        /* UVD clocks */
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, &value)) {
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value)) {
                if (!value) {
                        seq_printf(m, "UVD: Disabled\n");
                } else {
                        seq_printf(m, "UVD: Enabled\n");
-                       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, &value))
+                       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value))
                                seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
-                       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, &value))
+                       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value))
                                seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
                }
        }
        seq_printf(m, "\n");
 
        /* VCE clocks */
-       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, &value)) {
+       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value)) {
                if (!value) {
                        seq_printf(m, "VCE: Disabled\n");
                } else {
                        seq_printf(m, "VCE: Enabled\n");
-                       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, &value))
+                       if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value))
                                seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
                }
        }

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 8074386da36f83c4d81daf14e3c49b0109dbd1dd..81e6856ffa11426d9ff1204597432ed967b98a76 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -880,7 +880,7 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
        return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 }
 
-static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
+static int pp_dpm_read_sensor(void *handle, int idx, void *value)
 {
        struct pp_hwmgr *hwmgr;
        struct pp_instance *pp_handle = (struct pp_instance *)handle;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index a4cde3d778b85b7a859ed18712cd10c04622ad6a..edc3029df785fad83952aa6cfdbe5b1c891dcff4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1813,7 +1813,7 @@ static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
        return actual_temp;
 }
 
-static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
+static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value)
 {
        struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 
@@ -1841,7 +1841,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
        case AMDGPU_PP_SENSOR_GFX_SCLK:
                if (sclk_index < NUM_SCLK_LEVELS) {
                        sclk = table->entries[sclk_index].clk;
-                       *value = sclk;
+                       *((uint32_t *)value) = sclk;
                        return 0;
                }
                return -EINVAL;
@@ -1849,13 +1849,13 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
                tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
                        CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
                vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
-               *value = vddnb;
+               *((uint32_t *)value) = vddnb;
                return 0;
        case AMDGPU_PP_SENSOR_VDDGFX:
                tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
                        CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
                vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
-               *value = vddgfx;
+               *((uint32_t *)value) = vddgfx;
                return 0;
        case AMDGPU_PP_SENSOR_UVD_VCLK:
                if (!cz_hwmgr->uvd_power_gated) {
@@ -1863,11 +1863,11 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
                                return -EINVAL;
                        } else {
                                vclk = uvd_table->entries[uvd_index].vclk;
-                               *value = vclk;
+                               *((uint32_t *)value) = vclk;
                                return 0;
                        }
                }
-               *value = 0;
+               *((uint32_t *)value) = 0;
                return 0;
        case AMDGPU_PP_SENSOR_UVD_DCLK:
                if (!cz_hwmgr->uvd_power_gated) {
@@ -1875,11 +1875,11 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
                                return -EINVAL;
                        } else {
                                dclk = uvd_table->entries[uvd_index].dclk;
-                               *value = dclk;
+                               *((uint32_t *)value) = dclk;
                                return 0;
                        }
                }
-               *value = 0;
+               *((uint32_t *)value) = 0;
                return 0;
        case AMDGPU_PP_SENSOR_VCE_ECCLK:
                if (!cz_hwmgr->vce_power_gated) {
@@ -1887,11 +1887,11 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
                                return -EINVAL;
                        } else {
                                ecclk = vce_table->entries[vce_index].ecclk;
-                               *value = ecclk;
+                               *((uint32_t *)value) = ecclk;
                                return 0;
                        }
                }
-               *value = 0;
+               *((uint32_t *)value) = 0;
                return 0;
        case AMDGPU_PP_SENSOR_GPU_LOAD:
                result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
@@ -1901,16 +1901,16 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
                } else {
                        activity_percent = 50;
                }
-               *value = activity_percent;
+               *((uint32_t *)value) = activity_percent;
                return 0;
        case AMDGPU_PP_SENSOR_UVD_POWER:
-               *value = cz_hwmgr->uvd_power_gated ? 0 : 1;
+               *((uint32_t *)value) = cz_hwmgr->uvd_power_gated ? 0 : 1;
                return 0;
        case AMDGPU_PP_SENSOR_VCE_POWER:
-               *value = cz_hwmgr->vce_power_gated ? 0 : 1;
+               *((uint32_t *)value) = cz_hwmgr->vce_power_gated ? 0 : 1;
                return 0;
        case AMDGPU_PP_SENSOR_GPU_TEMP:
-               *value = cz_thermal_get_temperature(hwmgr);
+               *((uint32_t *)value) = cz_thermal_get_temperature(hwmgr);
                return 0;
        default:
                return -EINVAL;

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 31289a8d5cec095f923fe7c242b20cea379a51a7..c3f8e9d5656389ab71ddf40f01068466c0519f53 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3289,7 +3289,7 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
-static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
+static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value)
 {
        uint32_t sclk, mclk, activity_percent;
        uint32_t offset;
@@ -3299,12 +3299,12 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
        case AMDGPU_PP_SENSOR_GFX_SCLK:
                smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
                sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-               *value = sclk;
+               *((uint32_t *)value) = sclk;
                return 0;
        case AMDGPU_PP_SENSOR_GFX_MCLK:
                smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
                mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
-               *value = mclk;
+               *((uint32_t *)value) = mclk;
                return 0;
        case AMDGPU_PP_SENSOR_GPU_LOAD:
                offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr,
@@ -3314,16 +3314,16 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
                activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
                activity_percent += 0x80;
                activity_percent >>= 8;
-               *value = activity_percent > 100 ? 100 : activity_percent;
+               *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
                return 0;
        case AMDGPU_PP_SENSOR_GPU_TEMP:
-               *value = smu7_thermal_get_temperature(hwmgr);
+               *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
                return 0;
        case AMDGPU_PP_SENSOR_UVD_POWER:
-               *value = data->uvd_power_gated ? 0 : 1;
+               *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
                return 0;
        case AMDGPU_PP_SENSOR_VCE_POWER:
-               *value = data->vce_power_gated ? 0 : 1;
+               *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
                return 0;
        default:
                return -EINVAL;

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 4b4f5ff2f039351c27d68cc28bc382b75d50e0c4..97009110e011d48d86c2e1f0e046a636636fe368 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -359,7 +359,7 @@ struct amd_powerplay_funcs {
        int (*set_sclk_od)(void *handle, uint32_t value);
        int (*get_mclk_od)(void *handle);
        int (*set_mclk_od)(void *handle, uint32_t value);
-       int (*read_sensor)(void *handle, int idx, int32_t *value);
+       int (*read_sensor)(void *handle, int idx, void *value);
        struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx);
        int (*reset_power_profile_state)(void *handle,
                        struct amd_pp_profile *request);

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 768f81f365cac09cda1a2e05d5474bf3216afa23..fa3bf50eff822909365d889ce2ac8cb9bd6818c4 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -355,7 +355,7 @@ struct pp_hwmgr_func {
        int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
        int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
        int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
-       int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, int32_t *value);
+       int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value);
        int (*request_firmware)(struct pp_hwmgr *hwmgr);
        int (*release_firmware)(struct pp_hwmgr *hwmgr);
        int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,