pwm: mediatek: Fix PWM source clock selection

In original code, the PWM output frequency is not correct when set
bit<3>=1 to PWMCON register.

Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 5c11bc708a3cafe148d5311320d3b6bb46a41667..d08b5b3dca71127b3888519dda0cbbefafa0a2d5 100644 (file)
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
        if (clkdiv > 7)
                return -EINVAL;
 
-       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
+       mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
        mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
        mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);