GPIO01_IO05 is controlled by the LPSR iomux controller, so attach
the corresponding pin to this controller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
>;
};
- pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */
- >;
- };
-
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
>;
};
};
+
+&iomuxc_lpsr {
+ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */
+ >;
+ };
+};
\ No newline at end of file