ftgmac100: Fix potential ordering issue in NAPI poll
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Mon, 17 Apr 2017 22:37:05 +0000 (08:37 +1000)
committerDavid S. Miller <davem@davemloft.net>
Tue, 18 Apr 2017 18:11:09 +0000 (14:11 -0400)
We need to ensure the loads from the descriptor are done after the
MMIO store clearing the interrupts has completed, otherwise we
might still miss work.

A read back from the MMIO register will "push" the posted store and
ioread32 has a barrier on weakly aordered architectures that will
order subsequent accesses.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/faraday/ftgmac100.c

index 45b8267b81b7ccf142609a99123fff131e1b8158..95bf5e89cfd17b30d3543b33cb069f8aaee69d31 100644 (file)
@@ -1349,6 +1349,13 @@ static int ftgmac100_poll(struct napi_struct *napi, int budget)
                 */
                iowrite32(FTGMAC100_INT_RXTX,
                          priv->base + FTGMAC100_OFFSET_ISR);
+
+               /* Push the above (and provides a barrier vs. subsequent
+                * reads of the descriptor).
+                */
+               ioread32(priv->base + FTGMAC100_OFFSET_ISR);
+
+               /* Check RX and TX descriptors for more work to do */
                if (ftgmac100_check_rx(priv) ||
                    ftgmac100_tx_buf_cleanable(priv))
                        return budget;