ARM: imx: add common clock support for fixup div

One register may have several fields to control some clocks. It
is possible that the read/write values of some fields may map to
different real functional values, so writing to the other fields
in the same register may break a working clock tree. A real case
is the aclk_podf field in the register 'CCM Serial Clock Multiplexer
Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook
for divider clock which is called before writing a value to clock
registers to support this kind of divider clocks.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e20f22d58fd8f00618dd57732e5e9a17a25d88c3..92b91a22eb4d3a0e5b63ccb83cf20a04e01bd845 100644 (file)
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,7 +15,8 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
-                           clk-pfd.o clk-busy.o clk.o
+                           clk-pfd.o clk-busy.o clk.o \
+                           clk-fixup-div.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o

diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c
new file mode 100644 (file)
index 0000000..21db020
--- /dev/null
+++ b/arch/arm/mach-imx/clk-fixup-div.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
+#define div_mask(d)    ((1 << (d->width)) - 1)
+
+/**
+ * struct clk_fixup_div - imx integer fixup divider clock
+ * @divider: the parent class
+ * @ops: pointer to clk_ops of parent class
+ * @fixup: a hook to fixup the write value
+ *
+ * The imx fixup divider clock is a subclass of basic clk_divider
+ * with an addtional fixup hook.
+ */
+struct clk_fixup_div {
+       struct clk_divider divider;
+       const struct clk_ops *ops;
+       void (*fixup)(u32 *val);
+};
+
+static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
+{
+       struct clk_divider *divider = to_clk_div(hw);
+
+       return container_of(divider, struct clk_fixup_div, divider);
+}
+
+static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
+                                        unsigned long parent_rate)
+{
+       struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+
+       return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
+}
+
+static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *prate)
+{
+       struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+
+       return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
+}
+
+static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
+                           unsigned long parent_rate)
+{
+       struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+       struct clk_divider *div = to_clk_div(hw);
+       unsigned int divider, value;
+       unsigned long flags = 0;
+       u32 val;
+
+       divider = parent_rate / rate;
+
+       /* Zero based divider */
+       value = divider - 1;
+
+       if (value > div_mask(div))
+               value = div_mask(div);
+
+       spin_lock_irqsave(div->lock, flags);
+
+       val = readl(div->reg);
+       val &= ~(div_mask(div) << div->shift);
+       val |= value << div->shift;
+       fixup_div->fixup(&val);
+       writel(val, div->reg);
+
+       spin_unlock_irqrestore(div->lock, flags);
+
+       return 0;
+}
+
+static const struct clk_ops clk_fixup_div_ops = {
+       .recalc_rate = clk_fixup_div_recalc_rate,
+       .round_rate = clk_fixup_div_round_rate,
+       .set_rate = clk_fixup_div_set_rate,
+};
+
+struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
+                                 void __iomem *reg, u8 shift, u8 width,
+                                 void (*fixup)(u32 *val))
+{
+       struct clk_fixup_div *fixup_div;
+       struct clk *clk;
+       struct clk_init_data init;
+
+       if (!fixup)
+               return ERR_PTR(-EINVAL);
+
+       fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
+       if (!fixup_div)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_fixup_div_ops;
+       init.flags = CLK_SET_RATE_PARENT;
+       init.parent_names = parent ? &parent : NULL;
+       init.num_parents = parent ? 1 : 0;
+
+       fixup_div->divider.reg = reg;
+       fixup_div->divider.shift = shift;
+       fixup_div->divider.width = width;
+       fixup_div->divider.lock = &imx_ccm_lock;
+       fixup_div->divider.hw.init = &init;
+       fixup_div->ops = &clk_divider_ops;
+       fixup_div->fixup = fixup;
+
+       clk = clk_register(NULL, &fixup_div->divider.hw);
+       if (IS_ERR(clk))
+               kfree(fixup_div);
+
+       return clk;
+}

diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0e4e8bb261b945c1fb22d32b9e693592f17dfa41..51eb38538cc426946db30fe0fa6d861d95adea1b 100644 (file)
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -49,6 +49,10 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
                             u8 width, void __iomem *busy_reg, u8 busy_shift,
                             const char **parent_names, int num_parents);
 
+struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
+                                 void __iomem *reg, u8 shift, u8 width,
+                                 void (*fixup)(u32 *val));
+
 static inline struct clk *imx_clk_fixed(const char *name, int rate)
 {
        return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);