ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 4 Aug 2015 12:28:07 +0000 (14:28 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Wed, 12 Aug 2015 02:15:26 +0000 (11:15 +0900)
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r7s72100.dtsi

index 277e73c110e5d40c38953d3a3ea5079e6ec755f3..060c32cbd66923edbda896a9901a0a06495b70c4 100644 (file)
@@ -86,6 +86,7 @@
                        reg = <0xfcfe0000 0x18>;
                        clocks = <&extal_clk>, <&usb_x1_clk>;
                        clock-output-names = "pll", "i", "g";
+                       #power-domain-cells = <0>;
                };
 
                /* MSTP clocks */
                             <0 189 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 193 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 197 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 201 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 205 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 209 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 213 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 217 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
                clock-names = "sci_ick";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 240 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
                clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+               power-domains = <&cpg_clocks>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
                             <0 243 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
                clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+               power-domains = <&cpg_clocks>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
                             <0 246 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
                clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+               power-domains = <&cpg_clocks>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
                             <0 249 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
                clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+               power-domains = <&cpg_clocks>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
                             <0 252 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
                clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+               power-domains = <&cpg_clocks>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
                             <0 164 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
                clock-frequency = <100000>;
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
                clock-frequency = <100000>;
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 180 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
                clock-frequency = <100000>;
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                             <0 188 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
                clock-frequency = <100000>;
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
                interrupt-names = "tgi0a";
                clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
                clock-names = "fck";
+               power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 };