drm/i915: make A0 wa's applied to A1

Since A1 chips use the same GPU as A0, they need all the
same wa's in the i915 driver. Update some conditionals
to do this.

Signed-off-by: Tim Gore <tim.gore@intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1445856538-5417-1-git-send-email-tim.gore@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index c0281df52702e0427ec789053b163bbf2e8d970b..6ec7b2398200aceaced1f88b8816dc4ec19e2aa2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -309,7 +309,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 
        /* WaDisableMinuteIaClockGating:skl,bxt */
        if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-           IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+           IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
                                              ~GUC_ENABLE_MIA_CLOCK_GATING));
        }

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fd7b8c9fdfb490cc518486521e7635d0ef19ad19..28b1b74f76740722d7620a3f0f0f062843bc8fd6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -285,7 +285,7 @@ static bool disable_lite_restore_wa(struct intel_engine_cs *ring)
        struct drm_device *dev = ring->dev;
 
        return (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-               IS_BXT_REVID(dev, 0, BXT_REVID_A0)) &&
+               IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
               (ring->id == VCS || ring->id == VCS2);
 }
 
@@ -1313,7 +1313,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
 
        /* WaDisableCtxRestoreArbitration:skl,bxt */
        if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-           IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+           IS_BXT_REVID(dev, 0, BXT_REVID_A1))
                wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
 
        /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
@@ -1339,7 +1339,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
        /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
        if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
-           IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+           IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
                wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
                wa_ctx_emit(batch, index,
@@ -1349,7 +1349,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 
        /* WaDisableCtxRestoreArbitration:skl,bxt */
        if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-           IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+           IS_BXT_REVID(dev, 0, BXT_REVID_A1))
                wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
 
        wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd63bba147a45514941fb1a115b194682cda1764..c2e78994af4f91dd72981b96be647e40f8efb39c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4687,7 +4687,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
                        "on" : "off");
        /* WaRsUseTimeoutMode */
        if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
-           IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+           IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
                I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
                           GEN7_RC_CTL_TO_MODE |

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d6d2de19dca860c0c32adad8d9507c5668dcbf6..e0c527732606ae7dd3f8ef6a76281e203c73aa95 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1097,11 +1097,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 
        /* WaStoreMultiplePTEenable:bxt */
        /* This is a requirement according to Hardware specification */
-       if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
+       if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
                I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 
        /* WaSetClckGatingDisableMedia:bxt */
-       if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
+       if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
                                            ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
        }