[RAMEN9610-12373] fbdev: dpu20: added dqe software reset

Change-Id: I26a5e551d8fdbbec2109e1304de90c4ec5d6e5ec
Signed-off-by: ChiHun Won <chihun.won@samsung.com>

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c
index 06f5a5758305009de4f0fb2e8fb006a70ab730a2..e73c40163939ea81dd1523d0503d243160fa4a0f 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dqe_reg.c
@@ -42,6 +42,27 @@ u32 dqe_reg_get_hsc_on(void)
        return dqe_read_mask(DQECON, DQE_HSC_ON_MASK);
 }
 
+void dqe_reg_hsc_sw_reset(u32 id)
+{
+       u32 cnt = 5000; /* 3 frame */
+       u32 state;
+
+       dqe_write_mask(DQECON, ~0, DQE_HSC_SW_RESET_MASK);
+       decon_reg_update_req_dqe(id);
+
+       do {
+               state = dqe_read_mask(DQECON, DQE_HSC_SW_RESET_MASK);
+               cnt--;
+               udelay(10);
+       } while (state && cnt);
+
+       if (!cnt)
+               dqe_err("%s is timeout.\n", __func__);
+
+       dqe_dbg("dqe hsc_sw_reset:%d cnt:%d\n",
+               DQE_HSC_SW_RESET_GET(dqe_read(DQECON)), cnt);
+}
+
 void dqe_reg_set_hsc_pphc_on(u32 on)
 {
        dqe_write_mask(DQEHSC_CONTROL, ~0, HSC_PPHC_ON_MASK);

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h
index 4863eee82f2d8d31228431f21186e75522502432..93fdf62f8b1cdc46e48f4944d4fd3c14586b40f7 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/regs-dqe.h
@@ -4,6 +4,11 @@
 #define DQE_BASE                       0x2000
 /* DQECON_SET */
 #define DQECON                         0x0000
+#define DQE_APS_SW_RESET_MASK          (1 << 18)
+#define DQE_APS_SW_RESET_GET(_v)       (((_v) >> 18) & 0x1)
+#define DQE_HSC_SW_RESET_MASK          (1 << 16)
+#define DQE_HSC_SW_RESET_GET(_v)       (((_v) >> 16) & 0x1)
+
 #define DQE_HSC_ON_MASK                        (1 << 3)
 #define DQE_HSC_ON_GET(_v)             (((_v) >> 3) & 0x1)
 #define DQE_GAMMA_ON_MASK              (1 << 2)

diff --git a/drivers/video/fbdev/exynos/dpu20/decon_core.c b/drivers/video/fbdev/exynos/dpu20/decon_core.c
index f60150ebdda189c51bbf4dc2a8dcd965617ccdbc..b0f5b05ce7208696ac357b385bb4be47a1d2669a 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/decon_core.c
+++ b/drivers/video/fbdev/exynos/dpu20/decon_core.c
@@ -3979,6 +3979,7 @@ decon_init_done:
 
        decon->state = DECON_STATE_INIT;
 #if defined(CONFIG_EXYNOS_DECON_DQE)
+       decon_dqe_sw_reset(decon);
        decon_dqe_enable(decon);
 #endif
        return 0;

diff --git a/drivers/video/fbdev/exynos/dpu20/dqe.h b/drivers/video/fbdev/exynos/dpu20/dqe.h
index b72a265dd1119106e66b66f8fe226bd1b38b5fda..ca5123c01d0d5aa8a0e60dd940cf12b0c6b7a549 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/dqe.h
+++ b/drivers/video/fbdev/exynos/dpu20/dqe.h
@@ -99,6 +99,8 @@ struct dqe_device {
        struct dqe_ctx ctx;
 };
 
+extern int dqe_log_level;
+
 /* CAL APIs list */
 void dqe_reg_module_on_off(bool en_she, bool en_cgc, bool en_gamma,
                bool en_hsc, bool en_aps);
@@ -113,6 +115,7 @@ void dqe_reg_set_gamma_on(u32 on);
 u32 dqe_reg_get_gamma_on(void);
 void dqe_reg_set_hsc_on(u32 on);
 u32 dqe_reg_get_hsc_on(void);
+void dqe_reg_hsc_sw_reset(u32 id);
 void dqe_reg_set_hsc_pphc_on(u32 on);
 void dqe_reg_set_hsc_ppsc_on(u32 on);
 void dqe_reg_set_hsc_control(u32 val);
@@ -121,8 +124,6 @@ u32 dqe_reg_get_hsc_control(void);
 void dqe_reg_set_hsc_full_pxl_num(struct decon_lcd *lcd_info);
 u32 dqe_reg_get_hsc_full_pxl_num(void);
 void dqe_reg_set_aps_on(u32 on);
-void dqe_reg_hsc_sw_reset(u32 en);
-void dqe_reg_aps_sw_reset(u32 en);
 void dqe_reg_reset(u32 en);
 void dqe_reg_set_gammagray_on(u32 on);
 void dqe_reg_lpd_mode_exit(u32 en);
@@ -153,6 +154,7 @@ void dqe_reg_set_hsc_pphcgain_rgb(u32 r, u32 g, u32 b);
 void dqe_reg_set_hsc_pphcgain_cmy(u32 c, u32 m, u32 y);
 void dqe_reg_set_hsc_tsc_ycomp(u32 ratio, u32 gain);
 
+void decon_dqe_sw_reset(struct decon_device *decon);
 void decon_dqe_enable(struct decon_device *decon);
 void decon_dqe_disable(struct decon_device *decon);
 int decon_dqe_create_interface(struct decon_device *decon);

diff --git a/drivers/video/fbdev/exynos/dpu20/dqe_drv.c b/drivers/video/fbdev/exynos/dpu20/dqe_drv.c
index dbb39ed82086bb06aa0a8a7cb9f9e4e5dabcb69c..1a9e6997c72332d4d1669ddcf48f840ff68bdb1f 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/dqe_drv.c
+++ b/drivers/video/fbdev/exynos/dpu20/dqe_drv.c
@@ -1356,6 +1356,14 @@ err:
        return ret;
 }
 
+void decon_dqe_sw_reset(struct decon_device *decon)
+{
+       if (decon->id)
+               return;
+
+       dqe_reg_hsc_sw_reset(decon->id);
+}
+
 void decon_dqe_enable(struct decon_device *decon)
 {
        u32 val;