ARM: dts: imx6: RIoTboard explicitly define pad settings
authorIain Paton <ipaton0@gmail.com>
Sun, 13 Jul 2014 15:56:35 +0000 (16:56 +0100)
committerShawn Guo <shawn.guo@freescale.com>
Fri, 18 Jul 2014 08:49:46 +0000 (16:49 +0800)
Instead of relying on defaults or bootloader settings, explicitly define
all pad settings.

This resolves reported issues of no analogue audio output.

Signed-off-by: Iain Paton <ipaton0@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
arch/arm/boot/dts/imx6dl-riotboard.dts

index 80c926894d1e51824269dc85f6eed8dee8f6c495..43cb3fd76be764cdceb08efd949f47866ebe03e9 100644 (file)
        imx6-riotboard {
                pinctrl_audmux: audmuxgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x8000000
-                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x8000000
-                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x8000000
-                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x8000000
+                               MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
+                               MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
+                               MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
+                               MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
                                MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0         /* CAM_MCLK */
                        >;
                };
                        fsl,pins = <
                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
-                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x80000000
+                               MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0         /* AR8035 pin strapping: MODE#1: pull up */
                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0         /* AR8035 pin strapping: MODE#3: pull up */
                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0         /* AR8035 pin strapping: MODE#0: pull down */
-                               MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0xc0000000      /* GPIO16 -> AR8035 25MHz */
+                               MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8      /* GPIO16 -> AR8035 25MHz */
                                MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x130b0         /* RGMII_nRST */
-                               MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x80000000      /* AR8035 interrupt */
+                               MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x180b0         /* AR8035 interrupt */
                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
                        >;
                };
 
                pinctrl_led: ledgrp {
                        fsl,pins = <
-                               MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x80000000      /* user led0 */
-                               MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x80000000      /* user led1 */
+                               MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* user led0 */
+                               MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x1b0b1 /* user led1 */
                        >;
                };
 
                pinctrl_usbotg: usbotggrp {
                        fsl,pins = <
                                MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
-                               MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x80000000      /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
-                               MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x80000000
+                               MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
+                               MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x1b0b0
                        >;
                };
 
                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
-                               MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x80000000      /* SD2 CD */
-                               MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x80000000      /* SD2 WP */
+                               MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* SD2 CD */
+                               MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1f0b0 /* SD2 WP */
                        >;
                };
 
                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
-                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x80000000      /* SD3 CD */
-                               MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x80000000      /* SD3 WP */
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0 /* SD3 CD */
+                               MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1f0b0 /* SD3 WP */
                        >;
                };
 
                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
-                               MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x80000000      /* SD4 RST (eMMC) */
+                               MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x17059 /* SD4 RST (eMMC) */
                        >;
                };
        };