#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
+#include <mach/exynos-powermode.h>
#include <linux/platform_data/spi-s3c64xx.h>
#include <mach/exynos-fimc-is.h>
sdd->sfr_start = mem_res->start;
sdd->is_probed = 0;
sdd->ops = NULL;
+
+ sdd->idle_ip_index = exynos_get_idle_ip_index(dev_name(&pdev->dev));
+
if (pdev->dev.of_node) {
ret = of_alias_get_id(pdev->dev.of_node, "spi");
if (ret < 0) {
}
}
#else
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 0);
+
if (clk_prepare_enable(sdd->clk)) {
dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
ret = -EBUSY;
clk_disable_unprepare(sdd->clk);
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 1);
+
platform_set_drvdata(pdev, NULL);
spi_master_put(master);
/* Disable the clock */
clk_disable_unprepare(sdd->src_clk);
clk_disable_unprepare(sdd->clk);
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 1);
}
#endif
sdd->cur_speed = 0; /* Output Clock is stopped */
if (sci->domain == DOMAIN_TOP) {
/* Enable the clock */
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 0);
clk_prepare_enable(sdd->src_clk);
clk_prepare_enable(sdd->clk);
/* Disable the clock */
clk_disable_unprepare(sdd->src_clk);
clk_disable_unprepare(sdd->clk);
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 1);
#endif
}
if (__clk_get_enable_count(sdd->src_clk))
clk_disable_unprepare(sdd->src_clk);
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 1);
+
/* Free DMA channels */
if (sci->dma_mode == DMA_MODE && sdd->is_probed && sdd->ops != NULL) {
#ifdef CONFIG_ARM64
}
if (sci->domain == DOMAIN_TOP) {
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 0);
clk_prepare_enable(sdd->src_clk);
clk_prepare_enable(sdd->clk);
}
#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS) || defined(CONFIG_VIDEO_EXYNOS_FIMC_IS2)
else if (sci->domain == DOMAIN_CAM1 || sci->domain == DOMAIN_ISP) {
+ exynos_update_ip_idle_status(sdd->idle_ip_index, 0);
clk_prepare_enable(sdd->src_clk);
clk_prepare_enable(sdd->clk);