if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
- else if (hba->dev_quirks &
+ else if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_ERROR_IND_RECEIVED) {
+ if (hba->saved_uic_phy_err_cnt > 10) {
+ hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
+ hba->saved_uic_phy_err_cnt = 0;
+ } else
+ hba->saved_uic_phy_err_cnt++;
+ } else if (hba->dev_quirks &
UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
hba->uic_error |=
hba->errors = UFSHCD_ERROR_MASK & intr_status;
if (hba->errors)
ufshcd_check_errors(hba);
+ else
+ hba->saved_uic_phy_err_cnt = 0;
if (intr_status & UFSHCD_UIC_MASK)
ufshcd_uic_cmd_compl(hba, intr_status);
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP UFS_BIT(3)
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF UFS_BIT(5)
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT UFS_BIT(13)
+#define UIC_DATA_LINK_LAYER_ERROR_PA_ERROR_IND_RECEIVED UFS_BIT(14)
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002