ath9k: Process FATAL interrupts at first
authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Tue, 20 Nov 2012 12:59:59 +0000 (18:29 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Wed, 21 Nov 2012 19:16:01 +0000 (14:16 -0500)
FATAL and WATCHDOG interrupts should be processed first followed
by others.

Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/main.c

index 9594b6fcdf06317fcbd7f24e226a847f575b1a13..e59d8e3fcbc6ac201ddc8e62605e550b4a9f27d4 100644 (file)
@@ -494,17 +494,6 @@ irqreturn_t ath_isr(int irq, void *dev)
        if (status & SCHED_INTR)
                sched = true;
 
-#ifdef CONFIG_PM_SLEEP
-       if (status & ATH9K_INT_BMISS) {
-               if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
-                       ath_dbg(common, ANY, "during WoW we got a BMISS\n");
-                       atomic_inc(&sc->wow_got_bmiss_intr);
-                       atomic_dec(&sc->wow_sleep_proc_intr);
-               }
-       ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
-       }
-#endif
-
        /*
         * If a FATAL or RXORN interrupt is received, we have to reset the
         * chip immediately.
@@ -523,7 +512,15 @@ irqreturn_t ath_isr(int irq, void *dev)
 
                goto chip_reset;
        }
-
+#ifdef CONFIG_PM_SLEEP
+       if (status & ATH9K_INT_BMISS) {
+               if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
+                       ath_dbg(common, ANY, "during WoW we got a BMISS\n");
+                       atomic_inc(&sc->wow_got_bmiss_intr);
+                       atomic_dec(&sc->wow_sleep_proc_intr);
+               }
+       }
+#endif
        if (status & ATH9K_INT_SWBA)
                tasklet_schedule(&sc->bcon_tasklet);