clk: add gpio 12m and 24m for g12a/b

PD#165090: clk: add gpio 12m and 24m for g12a/b

Change-Id: I2a3e8ed2f318eb13375415939d6216b0f30103a3
Signed-off-by: Jian Hu <jian.hu@amlogic.com>

diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c
index 9a71296a601c599c4481bea8b2d9c5bd23d31a92..dd13b0e5ab285dea298b086cd8735751554665b8 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.c
+++ b/drivers/amlogic/clk/g12a/g12a.c
@@ -518,6 +518,49 @@ static struct clk_gate g12a_clk81 = {
        },
 };
 
+/* GPIO 24M */
+static struct clk_gate g12a_24m = {
+       .reg = (void *)HHI_XTAL_DIVN_CNTL,
+       .bit_idx = 11,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "g12a_24m",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "xtal" },
+               .num_parents = 1,
+               .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+       },
+};
+
+/* GPIO 12M */
+static struct clk_divider g12a_12m_div = {
+       .reg = (void *)HHI_XTAL_DIVN_CNTL,
+       .shift = 10,
+       .width = 1,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "g12a_12m_div",
+               .ops = &clk_divider_ops,
+               .parent_names = (const char *[]){ "xtal" },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_gate g12a_12m_gate = {
+       .reg = (void *)HHI_XTAL_DIVN_CNTL,
+       .bit_idx = 11,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "g12a_12m_gate",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "g12a_12m_div" },
+               .num_parents = 1,
+               .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+       },
+};
+
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
@@ -679,6 +722,9 @@ static struct clk_hw *g12a_clk_hws[] = {
        [CLKID_CPU_CLK]         = &g12a_cpu_clk.mux.hw,
 
        [CLKID_PCIE_PLL]        = &g12a_pcie_pll.hw,
+       [CLKID_24M]             = &g12a_24m.hw,
+       [CLKID_12M_DIV]         = &g12a_12m_div.hw,
+       [CLKID_12M_GATE]        = &g12a_12m_gate.hw,
 };
 /* Convenience tables to populate base addresses in .probe */
 
@@ -762,6 +808,8 @@ static struct clk_gate *g12a_clk_gates[] = {
        &g12a_vclk2_venclmmc,
        &g12a_vclk2_vencl,
        &g12a_vclk2_other1,
+       &g12a_24m,
+       &g12a_12m_gate,
 };
 
 static void __init g12a_clkc_init(struct device_node *np)
@@ -809,6 +857,8 @@ static void __init g12a_clkc_init(struct device_node *np)
        g12a_mpeg_clk_sel.reg = clk_base + (u64)g12a_mpeg_clk_sel.reg;
        g12a_mpeg_clk_div.reg = clk_base + (u64)g12a_mpeg_clk_div.reg;
 
+       g12a_12m_div.reg = clk_base + (u64)g12a_12m_div.reg;
+
        /* Populate base address for gates */
        for (i = 0; i < ARRAY_SIZE(g12a_clk_gates); i++)
                g12a_clk_gates[i]->reg = clk_base +

diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h
index a9ad55e239073708813a419a969cd1c4bb45160c..9cf4596c1a6653876f9a1a87cdd572b028dd3a11 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.h
+++ b/drivers/amlogic/clk/g12a/g12a.h
@@ -35,6 +35,7 @@
 
 #define HHI_PCIE_PLL_CNTL0             0x98 /* 0x26 offset in data sheet */
 #define HHI_PCIE_PLL_CNTL1             0x9c /* 0x27 offset in data sheet */
+#define HHI_XTAL_DIVN_CNTL             0xbc /* 0x2f offset in data sheet */
 //#define HHI_PCIE_PLL_CNTL6   0xf0 /* 0x3c offset in data sheet */
 
 #define HHI_HIFI_PLL_CNTL0             0xD8 /* 0x36 offset in data sheet */

diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h
index 5a4ec2bb9283c8bbbb5434bdb6add51715553f2b..37fdde18d44599754451f256ec22917ca5f7971e 100644 (file)
--- a/include/dt-bindings/clock/amlogic,g12a-clkc.h
+++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h
@@ -257,8 +257,13 @@
 #define CLKID_SPICC1_COMP        (CLKID_MISC_BASE + 7)
 #define CLKID_TS_COMP           (CLKID_MISC_BASE + 8)
 
+/*gpio 12M/24M */
+#define CLKID_24M               (CLKID_MISC_BASE + 9)
+#define CLKID_12M_DIV           (CLKID_MISC_BASE + 10)
+#define CLKID_12M_GATE          (CLKID_MISC_BASE + 11)
+
 /*G12B clk*/
-#define CLKID_G12B_ADD_BASE           (CLKID_MISC_BASE + 9)
+#define CLKID_G12B_ADD_BASE           (CLKID_MISC_BASE + 12)
 #define CLKID_CPUB_FCLK_P             (CLKID_G12B_ADD_BASE + 0)
 #define CLKID_CPUB_CLK                (CLKID_G12B_ADD_BASE + 1)
 /*G12B gate*/