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drm/tegra: sor - Change power down ordering
authorStéphane Marchesin <marcheu@chromium.org>
Fri, 23 May 2014 03:32:48 +0000 (20:32 -0700)
committerThierry Reding <treding@nvidia.com>
Mon, 9 Jun 2014 10:02:47 +0000 (12:02 +0200)
Lanes are powered up in decreasing order. Power them down in increasing
order for consistency.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/sor.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 735c76babdf2a727878b2939af3b687ce12dd7f5..f082ea22f32eb6abdb76be284734e76ca16fa88b 100644 (file)
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -748,7 +748,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
        tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 
        /* stop lane sequencer */
-       value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
+       value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
                SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
        tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);