GPIO: MIPS: lantiq: fix overflow inside stp-xway driver

The driver was using a 16 bit field for storing the shadow value of the shift
register cascade. This resulted in only the first 2 shift registeres receiving
the correct data. The third shift register would always receive 0x00.

Fix this by using a 32bit field for the shadow value.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-kernel@vger.kernel.org

diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
index e35096bf3cfb4f4faf1a46fed1ae79e2bd10e847..8bead0bb6459d917a7f2f52fe3bbfb1ecaf1edde 100644 (file)
--- a/drivers/gpio/gpio-stp-xway.c
+++ b/drivers/gpio/gpio-stp-xway.c
@@ -82,7 +82,7 @@ struct xway_stp {
        struct gpio_chip gc;
        void __iomem *virt;
        u32 edge;       /* rising or falling edge triggered shift register */
-       u16 shadow;     /* shadow the shift registers state */
+       u32 shadow;     /* shadow the shift registers state */
        u8 groups;      /* we can drive 1-3 groups of 8bit each */
        u8 dsl;         /* the 2 LSBs can be driven by the dsl core */
        u8 phy1;        /* 3 bits can be driven by phy1 */