KVM: arm64: Add the EL1 physical timer access handler

KVM traps on the EL1 phys timer accesses from VMs, but it doesn't handle
those traps. This results in terminating VMs. Instead, set a handler for
the EL1 phys timer access, and inject an undefined exception as an
intermediate step.

Signed-off-by: Jintack Lim <jintack@cs.columbia.edu>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index caa47ce7e006a6ddd9ffefa83bf29b27b71fd8e3..1cd3464ff88d8add7ff9b6f9acaf2da9f38041bf 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -820,6 +820,30 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
          CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),         \
          access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
 
+static bool access_cntp_tval(struct kvm_vcpu *vcpu,
+               struct sys_reg_params *p,
+               const struct sys_reg_desc *r)
+{
+       kvm_inject_undefined(vcpu);
+       return true;
+}
+
+static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
+               struct sys_reg_params *p,
+               const struct sys_reg_desc *r)
+{
+       kvm_inject_undefined(vcpu);
+       return true;
+}
+
+static bool access_cntp_cval(struct kvm_vcpu *vcpu,
+               struct sys_reg_params *p,
+               const struct sys_reg_desc *r)
+{
+       kvm_inject_undefined(vcpu);
+       return true;
+}
+
 /*
  * Architected system registers.
  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -1029,6 +1053,16 @@ static const struct sys_reg_desc sys_reg_descs[] = {
        { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
          NULL, reset_unknown, TPIDRRO_EL0 },
 
+       /* CNTP_TVAL_EL0 */
+       { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b000),
+         access_cntp_tval },
+       /* CNTP_CTL_EL0 */
+       { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b001),
+         access_cntp_ctl },
+       /* CNTP_CVAL_EL0 */
+       { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b0010), Op2(0b010),
+         access_cntp_cval },
+
        /* PMEVCNTRn_EL0 */
        PMU_PMEVCNTR_EL0(0),
        PMU_PMEVCNTR_EL0(1),