drm/radeon/kms: consolidate GART code, fix segfault after GPU lockup V2
authorJerome Glisse <jglisse@redhat.com>
Thu, 3 Nov 2011 15:16:49 +0000 (11:16 -0400)
committerDave Airlie <airlied@redhat.com>
Fri, 4 Nov 2011 10:39:51 +0000 (10:39 +0000)
After GPU lockup VRAM gart table is unpinned and thus its pointer
becomes unvalid. This patch move the unpin code to a common helper
function and set pointer to NULL so that page update code can check
if it should update GPU page table or not. That way bo still bound
to GART can be unbound (pci_unmap_page for all there page) properly
while there is no need to update the GPU page table.

V2 move the test for null gart out of the loop, small optimization

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_gart.c
drivers/gpu/drm/radeon/rs400.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rv770.c

index 7ce9c87e695eb5dade402e748ce9d268b58251d1..e4c384b9511c940559766f60ffe7e0f48337d97c 100644 (file)
@@ -894,7 +894,7 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
        u32 tmp;
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -946,7 +946,6 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int r;
 
        /* Disable all tables */
        WREG32(VM_CONTEXT0_CNTL, 0);
@@ -966,14 +965,7 @@ void evergreen_pcie_gart_disable(struct radeon_device *rdev)
        WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
index 722cfb39899230620f0622ca61644b3117dd261d..8402661fc206e9d212fabe18417cffebb0370d77 100644 (file)
@@ -935,7 +935,7 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -980,8 +980,6 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev)
 
 void cayman_pcie_gart_disable(struct radeon_device *rdev)
 {
-       int r;
-
        /* Disable all tables */
        WREG32(VM_CONTEXT0_CNTL, 0);
        WREG32(VM_CONTEXT1_CNTL, 0);
@@ -997,14 +995,7 @@ void cayman_pcie_gart_disable(struct radeon_device *rdev)
        WREG32(VM_L2_CNTL2, 0);
        WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
               L2_CACHE_BIGK_FRAGMENT_SIZE(6));
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void cayman_pcie_gart_fini(struct radeon_device *rdev)
index 4191eaf473816e30cfc9117cee6b751185dfd470..6d776626041996d29ccc8da64d5fbb93e79d464b 100644 (file)
@@ -577,7 +577,7 @@ int r100_pci_gart_init(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.ram.ptr) {
+       if (rdev->gart.ptr) {
                WARN(1, "R100 PCI GART already initialized\n");
                return 0;
        }
@@ -636,10 +636,12 @@ void r100_pci_gart_disable(struct radeon_device *rdev)
 
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
+       u32 *gtt = rdev->gart.ptr;
+
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
        }
-       rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
+       gtt[i] = cpu_to_le32(lower_32_bits(addr));
        return 0;
 }
 
index 33f2b68c680b349a5d9e097776d329fc047a37ef..400b26df652a8305c04d58f46db998672646b150 100644 (file)
@@ -74,7 +74,7 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
 
 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
-       void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+       void __iomem *ptr = rdev->gart.ptr;
 
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
@@ -93,7 +93,7 @@ int rv370_pcie_gart_init(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj) {
+       if (rdev->gart.robj) {
                WARN(1, "RV370 PCIE GART already initialized\n");
                return 0;
        }
@@ -116,7 +116,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
        uint32_t tmp;
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -154,7 +154,6 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int r;
 
        WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
        WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
@@ -163,14 +162,7 @@ void rv370_pcie_gart_disable(struct radeon_device *rdev)
        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
        tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rv370_pcie_gart_fini(struct radeon_device *rdev)
index ff3ae48aa1a7816d0c01dfe13c4fcd50304e8358..06f7682c87c7f15951a74b12cc4ea0ede7d0109c 100644 (file)
@@ -895,7 +895,7 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
        /* flush hdp cache so updates hit vram */
        if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
            !(rdev->flags & RADEON_IS_AGP)) {
-               void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+               void __iomem *ptr = (void *)rdev->gart.ptr;
                u32 tmp;
 
                /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
@@ -930,7 +930,7 @@ int r600_pcie_gart_init(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj) {
+       if (rdev->gart.robj) {
                WARN(1, "R600 PCIE GART already initialized\n");
                return 0;
        }
@@ -947,7 +947,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -1002,7 +1002,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
 void r600_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int i, r;
+       int i;
 
        /* Disable all tables */
        for (i = 0; i < 7; i++)
@@ -1029,14 +1029,7 @@ void r600_pcie_gart_disable(struct radeon_device *rdev)
        WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
        WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
        WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void r600_pcie_gart_fini(struct radeon_device *rdev)
index e94c6f18a157653c151240706b2306c2115345d0..b316b301152ff2f852d7a223d9a059e9a61eb84c 100644 (file)
@@ -307,30 +307,17 @@ int radeon_mode_dumb_destroy(struct drm_file *file_priv,
  */
 struct radeon_mc;
 
-struct radeon_gart_table_ram {
-       volatile uint32_t               *ptr;
-};
-
-struct radeon_gart_table_vram {
-       struct radeon_bo                *robj;
-       volatile uint32_t               *ptr;
-};
-
-union radeon_gart_table {
-       struct radeon_gart_table_ram    ram;
-       struct radeon_gart_table_vram   vram;
-};
-
 #define RADEON_GPU_PAGE_SIZE 4096
 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 #define RADEON_GPU_PAGE_SHIFT 12
 
 struct radeon_gart {
        dma_addr_t                      table_addr;
+       struct radeon_bo                *robj;
+       void                            *ptr;
        unsigned                        num_gpu_pages;
        unsigned                        num_cpu_pages;
        unsigned                        table_size;
-       union radeon_gart_table         table;
        struct page                     **pages;
        dma_addr_t                      *pages_addr;
        bool                            *ttm_alloced;
@@ -341,6 +328,8 @@ int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 void radeon_gart_table_vram_free(struct radeon_device *rdev);
+int radeon_gart_table_vram_pin(struct radeon_device *rdev);
+void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
 int radeon_gart_init(struct radeon_device *rdev);
 void radeon_gart_fini(struct radeon_device *rdev);
 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
@@ -348,6 +337,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
                     int pages, struct page **pagelist,
                     dma_addr_t *dma_addr);
+void radeon_gart_restore(struct radeon_device *rdev);
 
 
 /*
@@ -1445,8 +1435,6 @@ void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
 /* AGP */
 extern int radeon_gpu_reset(struct radeon_device *rdev);
 extern void radeon_agp_disable(struct radeon_device *rdev);
-extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
-extern void radeon_gart_restore(struct radeon_device *rdev);
 extern int radeon_modeset_init(struct radeon_device *rdev);
 extern void radeon_modeset_fini(struct radeon_device *rdev);
 extern bool radeon_card_posted(struct radeon_device *rdev);
index fdc3a9a54bf8e13cd6e4d9d475630cbec546b3b3..ba7ab79e12c1969793520a0ede951c675a52b469 100644 (file)
@@ -49,27 +49,27 @@ int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
                              rdev->gart.table_size >> PAGE_SHIFT);
        }
 #endif
-       rdev->gart.table.ram.ptr = ptr;
-       memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
+       rdev->gart.ptr = ptr;
+       memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size);
        return 0;
 }
 
 void radeon_gart_table_ram_free(struct radeon_device *rdev)
 {
-       if (rdev->gart.table.ram.ptr == NULL) {
+       if (rdev->gart.ptr == NULL) {
                return;
        }
 #ifdef CONFIG_X86
        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
            rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
-               set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
+               set_memory_wb((unsigned long)rdev->gart.ptr,
                              rdev->gart.table_size >> PAGE_SHIFT);
        }
 #endif
        pci_free_consistent(rdev->pdev, rdev->gart.table_size,
-                           (void *)rdev->gart.table.ram.ptr,
+                           (void *)rdev->gart.ptr,
                            rdev->gart.table_addr);
-       rdev->gart.table.ram.ptr = NULL;
+       rdev->gart.ptr = NULL;
        rdev->gart.table_addr = 0;
 }
 
@@ -77,10 +77,10 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                r = radeon_bo_create(rdev, rdev->gart.table_size,
                                     PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
-                                    &rdev->gart.table.vram.robj);
+                                    &rdev->gart.robj);
                if (r) {
                        return r;
                }
@@ -93,38 +93,46 @@ int radeon_gart_table_vram_pin(struct radeon_device *rdev)
        uint64_t gpu_addr;
        int r;
 
-       r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+       r = radeon_bo_reserve(rdev->gart.robj, false);
        if (unlikely(r != 0))
                return r;
-       r = radeon_bo_pin(rdev->gart.table.vram.robj,
+       r = radeon_bo_pin(rdev->gart.robj,
                                RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
        if (r) {
-               radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               radeon_bo_unreserve(rdev->gart.robj);
                return r;
        }
-       r = radeon_bo_kmap(rdev->gart.table.vram.robj,
-                               (void **)&rdev->gart.table.vram.ptr);
+       r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr);
        if (r)
-               radeon_bo_unpin(rdev->gart.table.vram.robj);
-       radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               radeon_bo_unpin(rdev->gart.robj);
+       radeon_bo_unreserve(rdev->gart.robj);
        rdev->gart.table_addr = gpu_addr;
        return r;
 }
 
-void radeon_gart_table_vram_free(struct radeon_device *rdev)
+void radeon_gart_table_vram_unpin(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                return;
        }
-       r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
+       r = radeon_bo_reserve(rdev->gart.robj, false);
        if (likely(r == 0)) {
-               radeon_bo_kunmap(rdev->gart.table.vram.robj);
-               radeon_bo_unpin(rdev->gart.table.vram.robj);
-               radeon_bo_unreserve(rdev->gart.table.vram.robj);
+               radeon_bo_kunmap(rdev->gart.robj);
+               radeon_bo_unpin(rdev->gart.robj);
+               radeon_bo_unreserve(rdev->gart.robj);
+               rdev->gart.ptr = NULL;
        }
-       radeon_bo_unref(&rdev->gart.table.vram.robj);
+}
+
+void radeon_gart_table_vram_free(struct radeon_device *rdev)
+{
+       if (rdev->gart.robj == NULL) {
+               return;
+       }
+       radeon_gart_table_vram_unpin(rdev);
+       radeon_bo_unref(&rdev->gart.robj);
 }
 
 
@@ -151,12 +159,14 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
                if (rdev->gart.pages[p]) {
                        if (!rdev->gart.ttm_alloced[p])
                                pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
-                                               PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+                                               PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
                        rdev->gart.pages[p] = NULL;
                        rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
                        page_base = rdev->gart.pages_addr[p];
                        for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
-                               radeon_gart_set_page(rdev, t, page_base);
+                               if (rdev->gart.ptr) {
+                                       radeon_gart_set_page(rdev, t, page_base);
+                               }
                                page_base += RADEON_GPU_PAGE_SIZE;
                        }
                }
@@ -199,10 +209,12 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
                        }
                }
                rdev->gart.pages[p] = pagelist[i];
-               page_base = rdev->gart.pages_addr[p];
-               for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
-                       radeon_gart_set_page(rdev, t, page_base);
-                       page_base += RADEON_GPU_PAGE_SIZE;
+               if (rdev->gart.ptr) {
+                       page_base = rdev->gart.pages_addr[p];
+                       for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
+                               radeon_gart_set_page(rdev, t, page_base);
+                               page_base += RADEON_GPU_PAGE_SIZE;
+                       }
                }
        }
        mb();
@@ -215,6 +227,9 @@ void radeon_gart_restore(struct radeon_device *rdev)
        int i, j, t;
        u64 page_base;
 
+       if (!rdev->gart.ptr) {
+               return;
+       }
        for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
                page_base = rdev->gart.pages_addr[i];
                for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
index 89a6e1ecea8deb595e8639a459f7aa477e5c287e..06b90c87f8f397012c82d631fa30a5bd57c5da5a 100644 (file)
@@ -77,7 +77,7 @@ int rs400_gart_init(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.ram.ptr) {
+       if (rdev->gart.ptr) {
                WARN(1, "RS400 GART already initialized\n");
                return 0;
        }
@@ -212,6 +212,7 @@ void rs400_gart_fini(struct radeon_device *rdev)
 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
        uint32_t entry;
+       u32 *gtt = rdev->gart.ptr;
 
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
@@ -221,7 +222,7 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
                ((upper_32_bits(addr) & 0xff) << 4) |
                RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
        entry = cpu_to_le32(entry);
-       rdev->gart.table.ram.ptr[i] = entry;
+       gtt[i] = entry;
        return 0;
 }
 
index 02e0390daa8ec4bc97dbfb760aa0c05ec12edbe7..481b99e89f6542d661c4f0697d413a6eff40f821 100644 (file)
@@ -414,7 +414,7 @@ int rs600_gart_init(struct radeon_device *rdev)
 {
        int r;
 
-       if (rdev->gart.table.vram.robj) {
+       if (rdev->gart.robj) {
                WARN(1, "RS600 GART already initialized\n");
                return 0;
        }
@@ -432,7 +432,7 @@ static int rs600_gart_enable(struct radeon_device *rdev)
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -495,20 +495,12 @@ static int rs600_gart_enable(struct radeon_device *rdev)
 void rs600_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int r;
 
        /* FIXME: disable out of gart access */
        WREG32_MC(R_000100_MC_PT0_CNTL, 0);
        tmp = RREG32_MC(R_000009_MC_CNTL1);
        WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (r == 0) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rs600_gart_fini(struct radeon_device *rdev)
@@ -526,7 +518,7 @@ void rs600_gart_fini(struct radeon_device *rdev)
 
 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 {
-       void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+       void __iomem *ptr = (void *)rdev->gart.ptr;
 
        if (i < 0 || i > rdev->gart.num_gpu_pages) {
                return -EINVAL;
index a09049d1590180b56c50f4e2cb6ee9600b79a8c1..a983f410ab89d7d549530d7b7c2f42287a6a7969 100644 (file)
@@ -124,7 +124,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -171,7 +171,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int i, r;
+       int i;
 
        /* Disable all tables */
        for (i = 0; i < 7; i++)
@@ -191,14 +191,7 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev)
        WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rv770_pcie_gart_fini(struct radeon_device *rdev)